16-bit Sigma Delta ADC

Overview

The IP is a 16-bit, delta-sigma (??), analog-to-digital converter (ADC). It comprises of a second-order discrete-time modulator followed by a third-order CIC decimation filter with programmable output rate.

Two operation modes are supported: single differential input (free-running mode) or multiplexing of up to 8 differential channels (incremental mode).

The IP integrates a reference voltage buffer and common-mode generation. It requires an external clock of 8 MHz for 4 kSps data rate. A slower clock may be used to reduce power consumption.

The modulator area is 322 x 276 µm. It consumes 87 µA from a 1.2 V or 1.5 V supply. The decimation filter is synthesised to 898 cells, which take roughly 0.02 mm2.

This IP is implemented on GF130LP CMOS process using 8 metal layers and baseline mask set (i.e., no MIM capacitors or thin-film resistors). Please get in touch to enquire about migration to other processes.

Key Features

Dual operation mode:
Single differential channel, free running
8 differential channels, incremental
Programmable 3rd-order CIC output data rate:
90 dB SNR at 20 Sps output
12.5-bit ENOB at 4 kSps
Low current consumption at maximum rate:
87 µA for the modulator
Small footprint: 0.11 mm2 (including the CIC)
May be supplied directly from cell battery:
1.20 V to 1.65 V analogue supply
1.20 V digital supply
Optional 1 V reference buffer
Optional 1 LSB dither injection
Operating temperature: –40 °C to 85 °C
Globalfoundries 130nm LP process

Benefits

Silicon proven
Low power
Small die area

Block Diagram

Applications

Sensing
Industrial sensor interfaces
Medical sensing
Sports and healthcare wearable devices
Battery/Low-power instrumentation
On-chip monitoring

Deliverables

Datasheet
Characterisation report
Flat netlist (cdl)
Decimation filter RTL code (SystemVerilog)
Layout view of modulator (gds2)
Synthesis constraints of decimation filter (sdc)
Abstract view of modulator (lef)
Behavioural model of complete ADC (Verilog)
Timing view of complete ADC (lib)
Integration guidelines and support

Technical Specifications

Foundry, Node

Globalfoundries 130LP

Maturity

Silicon Proven

Availability

Immediate

GLOBALFOUNDRIES

Silicon Proven: 130nm LP

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