15.5nA Current Bias with Enable - Ultra Low Voltage (0.9V), Ultra Low Power (50nW) Silterra 0.18 um

Overview

This macro-cell is an ultra low power general purpose current bias generator core designed for SilTerra 0.18µm CL180G CMOS technology. The circuit generates 7 × NMOS 15.5nA current branches and 1 × NMOS 7.75nA branch. The current bias is temperature compensated. The core is easily retargeted to any other CMOS technology due to high portability architecture.

Key Features

  • Ultra low power current bias
  • Ibias=15.5nA ±10% (without trimming)
  • Current consumption below 55nA in active mode
  • Flexible voltage operation: 1.0V–2.0V
  • Enable control
  • Indicative area: 0.0072mm2

Block Diagram

15.5nA Current Bias with Enable - Ultra Low Voltage (0.9V), Ultra Low Power (50nW) Silterra 0.18 um Block Diagram

Applications

  • Passive/active RFID tag ICs
  • Battery powered equipment
  • Energy Haversting ICs
  • Hearing Aids

Deliverables

  • Datasheet/Integration Guide
  • HDL Model
  • Flat GDSII database/LVS netlist
  • Customer Support

Technical Specifications

Foundry, Node
Silterra 0.18 um
Maturity
Silicon Proven
Silterra
Silicon Proven: 180nm
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Semiconductor IP