128 Channel Analog Front-End

Overview

Key Features

• Single-ended inputs for reducing the number of pads.
• Adjustable VGA input termination 50?, 100?, 200? or Hi-Z.
• A VGA with offset correction and an AGC loop.
• Input power level range from -20dBm to -10dBm.
• Data digitizing at 1GHz with 2-bit precision using zero-crossing and magnitude comparators.
• Offset correction for the zero-crossing comparator.
• Adjustable ADC conversion range.
• The TID and latch-up immune 45nm SOI CMOS (low K) process.

Benefits

• PMCC_XCM_64X64_A IP block includes 128 channels analog front-end. It converts analog input signals in the 10MHz-500MHz range to 2-bit digital data. The nominal sampling frequency is 1GHz. The IP block combines 16 groups of 8 analog front-ends in each group.

Block Diagram

Applications

• Radiometer, interferometer, spectrometer instruments.
• Radio astronomy.
• Cross-correlation systems.

Deliverables

• GDSII file
• Netlist for Spectre simulation
• Layout and Schematic (DRC & LVS) verification reports
• Complete IP block’s datasheet with integration/application notes
• Optional deliverables:
  • Library containing an entire hierarchy of the IP block’s schematic and layout cells
  • Extracted views containing parasitic components from layout
  • Verilog-A model replicating the IP block’s functionally
  • Simulation test-benches
  • Optional components specific to the IP block: biasing, specialized I/Os, glue-logic, transmission lines, etc.

Technical Specifications