12-bit 1-channel 44/70/90 MSPS pipeline ADC

Overview

The low-power high-speed 12-bit ADC employs high-performance differential pipeline architecture. The ADC consists of a core ADC, output logic, timing generation, reference currents circuits. The ADC requires: 1.7 ÷ 2 V analog supply, 1.7 ÷ 2 V digital supply, differential reference voltages 1.15 V and 0.65 V, common mode voltage 0.85 ÷ 1 V, reference current 9.9 ÷ 10.1 u? and differential input clock. The ADC supports standby mode which allows state with minimum power consumption. There is also the ability to configure the operating modes of the ADC by using digital registers.
The block is designed on TSMC 180 nm CMOS technology.

Key Features

TSMC 180 nm CMOS technology
High speed pipelined ADC
1-channel
Resolution 12 bit
Conversion rate 44 – 90 MHz
Different power supplies for digital (1.8 V) and analog (1.8 V) parts
Low standby current 0.2 u?
Low power dissipation:
- 59.4 mW at 44 MSPS
- 84.6 mW at 70 MSPS
Total Harmonic Distortion (THD):
- -70.6 dB at 44 MSPS and FIN = 1.9 MHz
- -70.1 dB at 70 MSPS and FIN = 1.9 MHz
Spurious-free dynamic range (SFDR)
- 72.7 dB at 44 MSPS and FIN = 1.9 MHz
- 73 dB at 70 MSPS and FIN = 1.9 MHz
Signal-to-noise ratio (SNR):
- 61.6 dB at 44 MSPS and FIN = 1.9 MHz
- 62.4 dB at 70 MSPS and FIN = 1.9 MHz
Compact die area 1.44 mm2
Portable to other technologies (upon request)

Applications

Optical networking
Test equipment
Portable ultrasound and digital beam-forming systems
Telecommunication systems
High quality imaging video systems
WiFi, WiMax
Mobile Communications
High quality imaging video systems
Data acquisition systems

Deliverables

Schematic or NetList
Abstract model (.lef and .lib files)
Layout view (optional)
Behavioral model (Verilog)
Extracted view (optional)
GDSII
DRC, LVS, antenna report
Test bench with saved configurations (optional)
Documentation

Technical Specifications

Foundry, Node

TSMC CMOS 180 nm

Maturity

silicon proven

Availability

Now

TSMC

Silicon Proven: 180nm

Request Info