100G Ethernet Solution (MAC + 100GBase-R PCS)

Overview

Key Features

• Implements the full 802.3 specification with preamble/SFD generation, frame padding generation, CRC generation and checking on transmit and receive respectively.
• Implements 802.3bd specification with ability to generate and recognize PFC pause frames (optional)
• Implements reconciliation sublayer functionality with start and terminate control characters alignment, error control character and fault sequence insertion and detection.
• Implements Deficit Idle Count (DIC) mechanism to ensure maximum possible throughput at the transmit interface.
• Support for VLAN tagged frames according to IEEE 802.1Q.
• Discards frames with mismatching destination address on receive (Except Broadcast and Multicast frames).
• Supports programmable promiscuous mode to omit MAC destination address checking on receive EMAC.
• CRC-32 generation and checking at high speed using an efficient pipelined CRC calculation algorithm.
• Implements 100GBase-R PCS core compliant with IEEE 802.3ba Specifications.
• Implements a 320-bit CGMII interface operating at 312.5MHz for 100G Ethernet.
• Implements 64b/66b encoding/decoding for transmit and receive PCS.
• Implements 100G scrambling/descrambling using 802.3ba specified polynomial 1 + x39 + x58
• Implements Multi-Lane Distribution (MLD) across 20 Virtual Lanes (VLs)
• Implements periodic insertion of Alignment Marker (AM) on the transmit path and deletion on the receive path
• Implements 66-bit block synchronization and Alignment Marker Lock machines as specified in 802.3ba specifications.
• Implements lane reordering to support reception of any virtual lane on any physical lane.
• Implements BIP-8 insertion/checking per Virtual Lane on transmit/receive respectively.
• Implements Inter Packet Gap (IPG) Insertion/Deletion for Alignment marker and clock compensation while maintaining a minimum of 1 byte IPG.
• Implements gear-box logic to convert 66-bit blocks to 20-bit for line side. The 20-bit interface operates at the transceiver reference clock.
• Implements programmable internal CGMII loop-back
• Implements Bit Error Rate (BER) monitor
• Implements skew compensation logic in order to realign all the virtual lanes and reassemble an aggregate 100G stream (with all 64b/66b blocks in the correct order)

Benefits

• Low logic utilization
• Interoperability verified and proven IP

Deliverables

• Compiled synthesizable binaries or encrypted RTL for the MAC and PCS cores
• Source code RTL (Verilog) for I2C, MDIO, RMON and Register-File blocks
• Self checking behavioral models and test benches for simulation
• Constraint files and synthesis scripts for design compilation
• A complete PCIe/UART host interface based reference design with:
• Design guide(s) and user manuals
• USA based technical support by developers

Technical Specifications