10/25/40/100G Ethernet PCS/PMA

Overview

The Chevin Technology PCS/ PMA is an IP core that simplifies the FPGA integration of Ultra low-latency 10/25/40/100G Ethernet connectivity in Intel and AMD Xilinx FPGAs.
Ultra-low latency is achieved by using only the PMA function in FPGA Multi-Gigabit transceivers and moving all PCS functions to code that is optimized for 10GBASE-R. This allows the data to take the shortest, and hence the lowest latency, path to and from the wire.
The PCS/ PMA is a PCS/ PHY block that can be used directly with Multi-Gigabit Transceivers PMA (SerDes & CDR logic) in any 10/25/40/100G capable FPGA for the lowest possible latency.

Key Features

Designed to IEEE 802.3ae-2002
Low Latency PCS/PMA (RTT) 109 ns
Small Footprint 2404 LUTs
Integrated 64b66b encoder/decoder
Integrated Scrambler/Descrambler
Gearbox for rate conversion
Fault management, BER monitoring
Clock Rate adaptation, TX/ RX
Detailed traffic analysis statistics collection
XGMII interface, 64bit @ 156.25MHz
XSBI interface, 32bit @ 322.265625MHz

Benefits

The application side can be driven by any XGMII compatible MAC with a 64bit interface at 156.25MHz.The PHY manages link encoding and scrambling, while adapting the data rate to the reference clocks.
A detailed statistics block provides a running count of frames sent and received with individual 64bit counters for frames, BER events, illegal codes and decode errors, which can be monitored through the Host Interface
Reference design available for Alpha-Data ADM-PCIE-KU3 or AMD Xilinx KC705 development board using standard software development tools when integrated with higher layers from Chevin Technology’s portfolio of IP blocks.

Block Diagram

Applications

Trade execution & monitoring
Data Storage & Capture systems
HPC / Big Data systems
Signal processing systems
Data Mining

Deliverables

Encrypted netlist/ source code for UltraScale AND 7 Series FPGAs
Datasheet & User Guide to assist integration
Reference Design on Alpha-Data ADM-KU3 and Xilinx KC705 development board
Simulation Test bench
Build scripts for ISE/Vivado
Support for integration into FPGA

Technical Specifications

Availability

Now

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