10/25/40/100Gbit/s Ethernet PCS/PMA

Overview

Smooth integration of TCP/IP and UDP/IP protocols in your FPGA

PGA Synthesisable 10/25/40/100 Gbit/s Ethernet PCS code for ultra-low latency 10/25/40/100Gbit/s connectivity 1025GBASE-R

The 10/25/40/100G PCS IP block simplifies FPGA integration of an ultra-fast 10/25/40/100Gbit/s Ethernet PCS Layer in FPGA

IEEE802.3by specification for coding/decoding using 64b66b rules, scrambling with a powerful polynomial and gearbox

Proven on Alpha-Data ADM-PCIE-8V3 board to reduce PCS latency down to 42.3ns/99ns between XGMII and XSBI interfaces.

The application side can be driven by any XGMII compatible MAC with a 64bit interface at 156.25MHz.The PHY manages link encoding and scrambling, while adapting the data rate to the reference clocks.
A detailed statistics block provides a running count of frames sent and received with individual 64bit counters for frames, BER events, illegal codes and decode errors, which can be monitored through the Host Interface
Reference design available for Alpha-Data ADM-PCIE-KU3 or AMD Xilinx KC705 development board using standard software development tools when integrated with higher layers from Chevin Technology’s portfolio of IP blocks.

Availability

Now