Smooth integration of TCP/IP and UDP/IP protocols in your FPGA
PGA Synthesisable 10/25/40/100 Gbit/s Ethernet PCS code for ultra-low latency 10/25/40/100Gbit/s connectivity 1025GBASE-R
The 10/25/40/100G PCS IP block simplifies FPGA integration of an ultra-fast 10/25/40/100Gbit/s Ethernet PCS Layer in FPGA
IEEE802.3by specification for coding/decoding using 64b66b rules, scrambling with a powerful polynomial and gearbox
Proven on Alpha-Data ADM-PCIE-8V3 board to reduce PCS latency down to 42.3ns/99ns between XGMII and XSBI interfaces.
