Overview
The Universal Media Access Controller (UMAC) ensures efficient data flow, low latency, and optimized power usage. CoMira Solutions Inc. introduces the 1.6T Ethernet UMAC IP, an advanced Ethernet MAC IP core designed to meet the demanding requirements of data centers and high-performance network systems.
The 1.6T Ethernet UMAC is designed for flexibility and supports multi-channel and multi-rate configurations, enabling efficient scalability across diverse network environments.
At its core, the 1.6T Ethernet UMAC integrates advanced MAC (Media Access Control), PCS (Physical Coding Sublayer), and FEC (Forward Error Correction) logic, delivering a versatile and high-performance networking solution.
Built according to the IEEE 802.3dj Ethernet standards, CoMira’s 1.6T Ethernet UMAC is a comprehensive, scalable, and energy-efficient solution that enables seamless, high-bandwidth communication for tomorrow’s connected world and today’s most data-intensive applications.
Key Features
- Simple programming and bringing up sequence matching previous UMAC generations
- Support for arbitrary mixed modes across channels and dynamic mode switching
- Support for 224G SerDes
- Standard and priority pause generation, termination, and pass-through
- Support for jumbo frames up to 16K bytes
- TX runt frame padding and RX runt frame stripping
- Counters and interrupts for MIBs and various MAC and PCS/FEC events
- Support for Ethernet Technology Consortium RS(272,257+1) low latency FEC in all modes that support RS(544,514)
- Programmable alignment marker periods and values
- Programmable SerDes bit error injection for simple FEC testing
- Programmable per-channel xMII TX->RX loopback and per-SerDes lane TX->RX parallel loopback
- Independent TX and RX programmable any-to-any SerDes lane remapping
Benefits
Supports all required MAC, PCS, and FEC features of the IEEE 802.3 standard.
Effortlessly supports massive data demands for AI, ML, and hyperscale cloud environments.
Integrates easily with user logic and SerDes.
The built-in FEC and seamless error handling of 1.6T UMAC IP ensure consistent, high-quality data streams.
Integration tested with CoMira.
Includes various standard and non-standard controls and statuses to quickly diagnose field issues.
Block Diagram
Applications
Data Centers.
AI Workloads.
Telecom networks.
High Performance Computing (HPC).
Cloud Storage & Networking.
Deliverables
System verilog design RTL.
IPXACT views for register maps.
ASIC Integration guide (AIG) for the ASIC implementers.
ASIC Constraints and supporting information.
Core Functional Specification.
Programmers Guide (PG) and register specification Relevant Application notes.
Technical Specifications
