最新USB 3.0、PCIe 2.0 和 SATA 3.0 Combo PHY IP 核，助力下一代连接小芯片组

June 10, 2024 – T2M^IP, the global independent semiconductor IP Cores provider & Technology experts, is pleased to announce the immediate availability of its partner’s Silicon Proven and mature USB 3.0, PCIe 2.0 and SATA 3.0 PHY IP Cores with a successful mass production track record in 22nm Ultra Low Power and 8nm advanced process technology in a wide range of major Fabs. This advanced PHY IP is poised to revolutionize data transfer solutions with its versatile compatibility and power-efficient design, making it ideal for a wide range of applications, from consumer electronics to high-performance computing systems.

Licensed to a host of Global customers, the Combo PHY IP cores integrates three essential high-speed interface standards: USB 3.0, PCIe 2.0, and SATA 3.0 offering extensive compatibility, meeting the full specifications of each protocol. This integration not only enhances device connectivity but also simplifies system design and reduces overall cost. This wide-ranging compatibility ensures that the PHY IP cores can seamlessly integrate into various systems, providing robust connectivity solutions for a multitude of applications. Furthermore, it is fully compatible with the PIPE3.1 interface specification, facilitating seamless integration into diverse system architectures.

One of the standout features of this Combo PHY IP is its configurable data rates, supporting 1.5G, 2.5G, 3G, 5G, and 6G. This flexibility caters to a range of application needs, from low-power devices to high-performance systems. Additionally, it supports both 16-bit and 32-bit parallel interfaces when encode/decode is enabled and a 20-bit parallel interface when bypassed, providing versatility in data processing and transmission. The PHY IP Cores includes PLL control, reference clock control, and built-in power gating, which collectively contribute to significant power savings without compromising performance. It is compatible with various reference clock frequencies, including a 100MHz differential reference clock input or output in PCIe mode, with optional Spread-Spectrum Clock (SSC) support. This capability enhances signal integrity by generating and receiving SSC from 5000ppm to 0ppm. Programmable transmit amplitude and de-emphasis further optimize signal transmission, ensuring reliable and efficient data transfer.

Enhanced detection functions include TX detect RX in PCIe and USB 3.0 modes, Beacon signal generation and detection in PCIe mode, and Low Frequency Periodic Signaling (LFPS) in USB 3.0 mode. The PHY IP cores also excels in power management, supporting L1 sub-state power management and RX low latency mode in SATA operation mode. Built-in testing capabilities, such as Loopback BERT and Multiple Pattern BIST Mode, ensure comprehensive and efficient testing of the PHY IP's functionality.

USB 3.0, PCIe 2.0 and SATA 3.0 Combo PHY IP Cores offers a powerful, flexible, and efficient solution for advanced connectivity needs in 22nm and 8nm SoCs. T2M ‘s broad silicon Interface IP Core Portfolio also includes HDMI, Display Port, MIPI (CSI, DSI UniPro, UFS, RFFE, I3C), PCIe, DDR, 1G Ethernet, V-by-One, programmable SerDes, OnFi and many more, available in major Fabs in process geometries as small as 7nm.

Availability: These Semiconductor Interface IP Cores are available for immediate licensing either stand alone or with pre-integrated Controllers and PHYs. For more information on licensing options and pricing please drop a request / MailTo

About T2M: T2M^IP is the global independent semiconductor technology experts, supplying complex semiconductor IP Cores, Software, KGD and disruptive technologies enabling accelerated development of your Wearables, IOT, Communications, Storage, Servers, Networking, TV, STB and Satellite SoCs. For more information, please visit: www.t-2-m.com