motor control IP
Filter
Compare
18
IP
from 10 vendors
(1
-
10)
-
DC motor controller - UMC 3.5um HV
- Area: 2.94mm2
-
Real-Time Microcontroller - Ultra-low latency control loops for real-time computing
- Reliable event driven computing is enabled by the unique MIPS M8500 real-time multithreaded architecture.
- The M8500 is an easy-to-use general-purpose microcontroller with advanced efficiency and performance for sub -10μs control loop algorithms.
- The M8500 is a turnkey closed loop control solution with functional safety options and end-to-end software solution.
-
Tensilica FloatingPoint KQ7/KQ8 DSPs
- VLIW parallelism issuing multiple concurrent operations per cycle
- 512-bit and 1024-bit SIMD
- IEEE 754 vector floating-point (HP, SP, DP)
- Performance-optimized fused multiply-add (FMA)
-
Tensilica FloatingPoint KP1/KP6 DSPs
- VLIW parallelism issuing multiple concurrent operations per cycle
- Xtensa LX Secure Mode
- 128-bit and 512-bit SIMD
- IEEE 754 vector floating-point
-
Pulse Width Modulator
- The PWM IP core implements a compact and highly flexible Pulse Width Modulator. The core generates a repeated pattern of pulse trains of run-time configurable period and duty cycle.
- Those pulse trains can be used in a wide variety of applications including but not limited to motor control and LED dimming. They can also be filtered with a lowpass filter to implement Digital to Analog Converters (DAC).
-
E34 Standard RISC V Core
- Fully compliant with the RISC-V ISA specification
- RV32IMAFC Support
- RV32I - 32-bit RISC-V with 32 integer registers
- Integer Multiplication and Division (M) support
-
E24 High-performance microcontroller with hardware support
- RISC-V ISA - RV32IMAFC
- Machine and User Mode with 4 Region Physical Memory Protection
- 3-stage pipeline with Simultaneous Instruction and Data Access
- 2 Banks of Tightly Integrated Memory
-
Low power 32-bit processor with lightweight computing power
- Instruction set: T-Head ISA (32-bit/16-bit variable-length instruction set);
- Pipeline: 3 to 4-stage variable length pipeline;
- General register: 32 32-bit GPRs;
- Bus interface: Tri-bus (instruction bus + data bus + system bus);
-
Full-featured Real-time Application Processor
- Caches for fast code and data accesses
- Local Memories for deterministic code and data accesses
- IEEE754-compliant FPU coprocessor
- Memory Protection Unit (MPU) for secure RTOS
-
Arm Cortex-M7
- Optional instruction and data TCMs up to 16MB - Fast access to critical code and data via a dedicated bus. Increases responsiveness to critical events.
- Harvard instruction cache and data cache on 64-bit AMBA 4 AXI interface - Optimises access to large external memories or slow peripherals, reducing latency. Instruction and data caches are optional and separately configurable from 4KB to 64KB.
- SIMD, saturating arithmetic, fast MAC - Powerful instruction set for accelerating DSP applications, built right into the processor. A highly optimised DSP library built using these instructions is available free-of-charge from the Arm website.
- Powerful debug and non-obtrusive real-time trace, with optional full data trace - Comprehensive debug and trace features dramatically improve developer productivity. It is extremely efficient to develop embedded software with proper debug.
