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Search (12)
Compare 12 IP from 8 vendors (1 - 10)
  • Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
    • An experimental Z1010 heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs has been ported to the GlobalFoundries GF12LP process.
    • The picture below shows the full layout of the experimental architecture. The official Z1010 standard will include a different ratio of LUTs, DSPs, and BRAM.
    Block Diagram -- Heterogeneous eFPGA architecture with LUTs, DSPs, and BRAMs on GlobalFoundries GF12LP
  • eFPGA on GlobalFoundries GF12LP
    • All Platypus eFPGA hardened IP cores are backed up by an open architecture guarantee. Complete machine readable descriptions of standard architectures can be found in the Logiklib open source repository.
    • The Z1000 standard eFPGA architecture has been ported to the GlobalFoundries GF12LP process.
    Block Diagram -- eFPGA on GlobalFoundries GF12LP
  • eFPGA Hard IP Generator
    • Combination of over 30 years of programmable logic experience and expertise with proven standard ASIC design methodologies to create an eFPGA IP generator that can create and deliver a domain-specific eFPGA IP in as little as four weeks.
    Block Diagram -- eFPGA Hard IP Generator
  • eFPGA
    • Customize Vega to suit your needs
    • Accelerate your processor with Vega eFPGA
    • Seamlessly integrate and verify Vega IP into your SoC design
    • Enhance flexibility with on-chip FPGA functionality
    Block Diagram -- eFPGA
  • Radiation-Hardened eFPGA
    • Radiation-Hardened by Design (RHBD): Built to operate in space and defense applications, ensuring reliability under extreme conditions.
    • Customizable eFPGA IP: Tailored to specific mission requirements with adaptability to various process nodes and foundries.
    • High Reliability: Designed to withstand Total Ionizing Dose (TID) and Single Event Effects (SEE).
  • eFPGA Soft IP
    • These eFPGA IP cores offer designers the flexibility to tailor resources to their application requirements, available as either Soft RTL or Hard GDSII IP.
    • Our standard-cell-based approach facilitates rapid porting to new process geometries or variants, including industrial and rad-hard grade versions.
    Block Diagram -- eFPGA Soft IP
  • Embedded FPGA
    • 75% lower power
    • 90% lower cost
    • 100× lower latency
    Block Diagram -- Embedded FPGA
  • Embedded FPGA
    • Fully integrated into RTL SOC design flow
    • Highly scalable and customizable
    • Technology independent
    Block Diagram -- Embedded FPGA
  • Video Tracking FPGA IP core for Xilinx and Altera
    • MAIN PARAMETERS
    • High processing speed. One video frame processing time: for rectangle 128x128 pixels – 25 ms; for rectangle 128x64 pixels – 13 ms; for rectangle 64x64 pixels – 6,5 ms.
    • Objects tracking from 8x8 pixels to 128x128 pixels and more. Object part tracking.
    • Tracking of objects of very low contrast (from 10%) on a complex background in terms of interference.
  • Video Tracking FPGA IP core for Xilinx and Altera
    • Tracking up to 80 fps at core clock frequency 300 MHz and object size of 128x128 pixels.
    • The IP core implements 1 tracking channel. If sever-al channels are required, several cores need to be used.
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Semiconductor IP