Vision processor IP

Multi-sensor interface with up to 20-bit linear video input
Up to 8 independent camera sources of max resolution 48 Megapixels / 8K (8192 x 6144)

ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

32 to 864TOPs
(Dual, Quad, Octo Core) Up to 256K MACs
Hybrid Von Neuman + 2D SIMD matrix architecture
64b Instruction word, single instruction issue per clock
7-stage, in-order pipeline
Scalar / vector / matrix instructions modelessly intermixed with granular predication