V-by-one hs IP

Compare 17 IP from 8 vendors (1 - 10)

V-By-One HS Receiver PHY
- Next generation HD interface with low EMI
- Fully comply with V-By-One HS V1.3 electrical specification
- Low power consumption for multiple lane application
- Compact size: 0.1mm2 per lane including PMU and IO PAD
FTVBOTXALL010 is a V-by-One transmitter designed for applications that take ultra-low power dissipation and high data transfer rate. This IP is compliant with the V-By-One HS Standard, Ver. 1.3. It transfers the packed packet from direct the video stream
VBYONE Verification IP
- Follows VByOne specification as v1.2/1.3/1.4/1.5
- Support transmitter and Receiver Mode.
- Supports upto 32 serial lanes.
- Supports all byte lengths, color depths, and resolutions.
V-By-One Transmitter IIP
- Compliant with VByOne specification 1.2/1.3/1.4.
- Full VBYONE Transmit functionality.
- Supports 1 to 8 lanes. If needed, we can support custom lane configuration.
- Supports all byte lengths.
V-By-One Receiver IIP
- Compliant with VByOne specification 1.2/1.3/1.4.
- Full VBYONE Receive functionality.
- Supports 1 to 8 lanes. If needed, we can support custom lane configuration.
- Supports all byte lengths.
V-by-One Rx IP, Silicon Proven in 40G
- Wide-range data rate, up to 1Gbps, and the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
- 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
- DC coupling mode
- Multi-channel shared offset
V-by-One Tx IP, Silicon Proven in 40G
- Wide-range data rate, up to 1Gbps, the associated
- clock is DDR clock (1/2 of the data rate, up to 500MHz)
- 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
- DC coupling mode
V-by-One/ LVDS Tx IP, Silicon Proven in SMIC 40LL
- LVDS compliant Tx
- 4 groups of 4-Data
- 1-Clock channels Each lane/group can be turned on/off individually Data/Clock can be assigned to any lane within the group
- Differential polarity can be flip per lane
V-by-One Rx IP, Silicon Proven in SMIC 40LL
- Wide-range data rate, up to 1Gbps, and the associated clock is DDR clock (1/2 of the data rate, up to 500MHz)
- 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
- DC coupling mode
- Multi-channel shared offset
V-by-One Tx IP, Silicon Proven in SMIC 40LL
- 16 channels total 128 bits of parallel data, each channel has a bit width of 8 bits
- DC coupling mode
- Multi-channel shared offset
- Built-in transmitter terminal impedance, no need for off-chip components

V-by-One HS IP