High-speed serial interface compliant with V-by-One® HS plus standard
IP core for FPGAs that supports “V-by-One® HS plus Standard”, the next-generation high-speed interface standard technology developed by THine Electronics Inc.
V-by-One® HS plus Tx/Rx IP is an IP to enable Altera® FPGAs to send and receive signals compatible with the latest “V-by-One® HS plus Standard”.
Overview of V-by-One® HS plus Standard
V-by-One® HS plus is a next-generation high-speed interface standard proposed and developed by THine Electronics, Inc.. Key points are as follows:
- Maximum transmission speed of 8Gbps/lane
- Twice the speed of conventional technologies, supporting higher resolutions for LCD TVs, OLED TVs, etc., and higher refresh rates for gaming applications.
- Cable reduction and slimming
- Contributes to reduction in system cost and power consumption through cable reduction and slimming of transmission paths inside equipment.
- Ensuring backward compatibility
- Two modes are defined: "HS Mode," which has backward compatibility with conventional V-by-One® HS, and "HS plus Mode", which enables transmission at up to 8Gbps/lane.
- Improved user convenience
- Following the basic protocol and design concept of the existing V-by-One® HS, this next-generation high-speed interface standard has low hurdles for introduction.
IP Release Schedule (by Supported FPGA)
Altera® Devices
- Arria® 10 GX FPGA
- Cyclone® 10 GX FPGA
- Agilex™ 7 FPGA *Supported on F-Tile products.
- Agilex™ 5 FPGA *Please contact us.
