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UFS 2.1 IP

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Compare 13 IP from 6 vendors (1 - 10)
  • UFS 2.1 Stack & Driver
    • Compliant with JEDEC UFS HCI 2.0 and MIPI UniPro Specification version 1.6
    • Portability in choice of OS, processors and hardware
    • Easy-to-use interface for applications
    • Fully documented generic device operation API
    Block Diagram -- UFS 2.1 Stack & Driver
  • UFS 2.1 Host Controller IP
    • JEDEC UFS 2.0 and UFS HCI 2.0 Compliant
    • Supports high performance M-PHY v3.0 type-1
    • 2 lanes @ 5.9 Gbps per lane
    • UniPro v1.6 link layer
    • Definable write-protect group size
    Block Diagram -- UFS 2.1 Host Controller IP
  • UFS 2.1 Device Controller IP
    • The UFS 2.1 Device controller uses an M-PHY® 3.1 Adapter Layer backed by a UniPro v1.6 Link layer controller as per the specification.
    • The UFS compliant IP cores are interface building blocks that simplify interconnect architectures in mobile platforms.
    Block Diagram -- UFS 2.1 Device Controller IP
  • UFS 3.1 Silicon Proven 2.1 HOST
    • Compliant with UFS Specification v2.x, 3.x
    • Supports up to 2-lanes (restricted by Standard) running at HS-G3 (5.8Gbps)
    • AXI Support
    • All UPIU Processing
    Block Diagram -- UFS 3.1 Silicon Proven 2.1 HOST
  • UFS 3.1 Silicon Proven 2.1 Device, Host
    • Compliant with UFS Specification v2.x, 3.x
    • Supports up to 2-lanes (restricted by Standard) running at HS-G3 (5.8Gbps)
    Block Diagram -- UFS 3.1 Silicon Proven 2.1 Device, Host
  • UFS 3.0 Device
    • UFS 3.0 is the next specification update pending from JEDEC.
    • Arasan will offer UFS 3.0 compatible Host and Device Controllers in late Q2 2017 to select customers.
  • UFS 3.1 Device
    • UFS 3.1 is the next specification update pending from JEDEC.
    • Arasan will offer UFS 3.1 compatible Host and Device Controllers in late Q2 2017 to select customers.
  • UFS Controller - Verifies compliance and performance of UFS interfaces in SoCs
    • The UFS Controller Verification IP (VIP) ensures proper operation and compliance of UFS interfaces in SoC designs. It supports UFS 2.0, 2.1, 3.0, and 3.1 standards, enabling efficient validation of high-speed data transfers and power management.
    • The VIP is critical for validating UFS controllers in a wide range of applications, from AI/ML systems to mobile devices and automotive infotainment. It ensures optimal performance, reliability, and seamless integration in diverse environments
    Block Diagram -- UFS Controller - Verifies compliance and performance of UFS interfaces in SoCs
  • Simulation VIP for UFS
    • Interfaces
    • DPDN I/F and RMMI I/F when used with UniPro VIP. CPort signaling pin I/F and CPort message using transactions
    • UTP Layer - UPIUs
    • NOP IN, NOP OUT, Query Request/ Response, Task Management Request/ Response, Command, Response, Data Out, Data In
    Block Diagram -- Simulation VIP for UFS
  • UFS Synthesizable Transactor
    • Full UFS Host and Device functionality
    • Supports UFS 2.1 draft specification
    • Supports high performance M-PHY type-1
    • Supports full UFS Host and Device functionality
    Block Diagram -- UFS Synthesizable Transactor
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