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TSMC 12FFC IP

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Compare 109 IP from 8 vendors (1 - 10)
  • DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
    • Supported DRAM type: DDR3L/DDR4/LPDDR4
    • Maximum controller clock frequency of 400MHz resulting in maximum DRAM data rate of 1866Mbps
    • Interface: SSTL135/POD12/LVSTL
    • Data path width scales in 32-bit increment
    Block Diagram -- DDR4/ LPDDR4/ DDR3L PHY IP - 3200Mbps (Silicon Proven in TSMC 12FFC)
  • 512x8 Bits OTP (One-Time Programmable) IP, TSMC 12FFC 0.8V/1.8V Process
    • Fully compatible with TSMC 12FFC 0.8V/1.8V
    • Low voltage: 0.8 V ± 10% for read and 1.1 V ± 5% for program
    • High speed: 10µs program time per bit, and 50ns read 8-bit at a time
  • USB-C 3.1/DP TX PHY for TSMC 12FFC, North/South Poly Orientation
    • Industry’s only USB Type-C IP solution consisting of USB-C 3.1/DisplayPort 1.3 Tx PHYs, USB-C 3.1/DisplayPort 1.3 Tx controllers with HDCP 2.2 and HDCP 1.4 content protection, verification IP, IP subsystems, IP prototyping kits, and IP software development kits
    • Solution supports USB Type-C, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.3 Tx supporting RBR, HBR1, HBR2 and HBR3 bitrates
    • Controllers support Device, Host, and Dual-Role Device USB-C 3.1 as well as DisplayPort 1.3 Tx with HDCP 2.2 content protection
    Block Diagram -- USB-C 3.1/DP TX PHY for TSMC 12FFC, North/South Poly Orientation
  • DisplayPort 1.4 TX PHY, TSMC 12FFC, North/South Poly Orientation
    • USB-IF certified DesignWare USB 3.1 solution
    • VESA certified DesignWare DisplayPort 1.4 Tx solution
    • Industry’s only USB Type-C IP solution consisting of USB-C 3.1/DisplayPort 1.4 TX PHYs, USB-C 3.1/DisplayPort 1.4 TX controllers with HDCP 2.2 and HDCP 2.2 content protection, verification IP, and IP subsystems
    • Solution supports USB Type-C, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.4 TX supporting RBR, HBR1, HBR2 and HBR3 bitrates
    Block Diagram -- DisplayPort 1.4 TX PHY, TSMC 12FFC, North/South Poly Orientation
  • Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC 12FFC X8, North/South (vertical) poly orientation
    • 16-lane TX and RX square macros for placement in any edge of the die
    • Supports 2.5G to 112G data rates, enabling very high bandwidth per mm of beachfront for die-to-die and die-to-optical engine connectivity
    • Implements NRZ and PAM-4 signaling
    • Meets the performance, efficiency, and reliability requirements of die-to-die interconnects
    Block Diagram -- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC 12FFC X8, North/South (vertical) poly orientation
  • Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC 12FFC X16, North/South (vertical) poly orientation
    • 16-lane TX and RX square macros for placement in any edge of the die
    • Supports 2.5G to 112G data rates, enabling very high bandwidth per mm of beachfront for die-to-die and die-to-optical engine connectivity
    • Implements NRZ and PAM-4 signaling
    • Meets the performance, efficiency, and reliability requirements of die-to-die interconnects
    Block Diagram -- Die-to-Die, 112G Ultra-Extra Short Reach PHY Ported to TSMC 12FFC X16, North/South (vertical) poly orientation
  • LPDDR5/4/4X PHY - TSMC 12FFC
    • Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
    • Support for data rates up to 6400 Mbps
    • Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
    • DFI 5.0 controller interface
    Block Diagram -- LPDDR5/4/4X PHY - TSMC 12FFC
  • DDR5/4 PHY - TSMC 12FFC
    • Supports JEDEC standard DDR5 and DDR4 SDRAMs
    • High-performance DDR PHY supporting data rates up to 8400 Mbps
    • PHY independent, firmware-based training using an embedded calibration processor
    • Supports up to 4 trained states/ frequencies with <3μs switching time
    Block Diagram -- DDR5/4 PHY - TSMC 12FFC
  • 25G PHY, TSMC 12FFC x8 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G PHY, TSMC 12FFC x8 North/South (vertical) poly orientation
  • 25G PHY, TSMC 12FFC x4 North/South (vertical) poly orientation
    • Supports 1.25 to 25.8 Gbps data-rate
    • Supports PCI Express 4.0 with lane margining, 1G to 100G Ethernet, CCIX, and SATA protocols
    • Supports x1 to x16 macro configurations with aggregation and bifurcation
    • Spread Spectrum Clock (SSC), ` PCIe Separate Refclk Independent SSC (SRIS) and power management features
    Block Diagram -- 25G PHY, TSMC 12FFC x4 North/South (vertical) poly orientation
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