TLS accelerator IP
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11
IP
from 5 vendors
(1
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10)
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Secure-IC's Securyzr(TM) TLS Handshake Hardware Accelerator
- RSA, ECC and more
- > 1 GHz in 16nm
- 400-500 MHz on mid-range/high-end FPGA
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Secure-IC's Securyzr™ Public Key Crypto Engine
- ASIC & FPGA
- RSA, ECC and more
- 100% CPU offload
- DPA countermeasures
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Unified Hardware IP for Post-Quantum Cryptography based on Kyber and Dilithium
- Turn-key implementations of the NIST FIPS recommended CRYSTALS post-quantum for key encapsulation (KEM) and digital signature algorithm (DSA)
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Poly1305 core
- Processing of a 128-bit dataword in as low as 4 clock cycles
- Different processing architectures offering different balances between throughput/area
- Fixed time processing for resistance against timing attacks
- Simple register-based interface
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ChaCha20 stream cipher core
- Simple register based interface
- Processing of 64-bytes in as low as 13 clock cycles
- Selection between High Throughput or Low Gate-Count architectures
- Real-time selection between key generation or cipher/decipher modes
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Combined ChaCha20 and Poly1305 core
- Multiple processing modes:
- Chacha20 processing of 64-bytes in as low as 13 clock cycles
- Poly1305 processing of 16-bytes in as low as 4 clock cycles
- Different processing architectures offering different balances between throughput/area
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In-line Multi-Protocol Cipher Engine
- IPSec (IPv4 and IPv6):
- and 6379),
- MACsec
- 802.1AE
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nQrux™ Confidential Computing Engine (CCE)
- Complete physical isolation of code & data
- Secure code & data transmission with TLS 1.3 Quantum-safe crypto option
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Integrated Secure Element (iSE) for industrial IoT, factory automation, and AI devices
- Easy to integrate
- Tunable solution
- Fully digital
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Multi-Protocol Crypto Engine with Classification
- IPsec Classification:
- IPsec transformation:
- SSLv3.0 / TLSv1.0 / TLSv1.1 / TLSv1.2 / TLSv1.3:
- DTLS v1.0 / DTLS v1.2 / DTLS v1.3