TLS accelerator IP
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12
IP
from
8
vendors
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10)
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PKC Multi Hardware Accelerator IP
- The PKC Multi hardware accelerator is a secure connection engine that can be used to offload the compute intensive Public Key operations (Diffie-Hellman Key Exchange, Signature Generation and Verification), widely used for High-performance TLS Handshake.
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High-Speed Elliptic Curve Cryptography Accelerator for ECDH and ECDSA
- Fully digital design
- Portable to any ASIC or FPGA technology
- Fully standard compliant
- Easy to integrate
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Single instance HW Lattice PQC ultra accelerator
- PQPerform-Flare is a powerful hardware-based FIPS 140-3 CAVP-certified product, designed for high throughput and low latency PQC.
- It adds PQC for applications that typically handle a large number of transactions, such as high-capacity network hardware applications and secure key management HSMs.
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HMAC-SHA256 cryptographic accelerator
- Hardware Root of Trust
- Widely used password hash algorithm
- Security Critical HTTP, SSL, TLS
- Key storage in Private memory
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HMAC-SHA256 Secure Core - Hardware Accelerator for SHA-2 and HMAC with Low Latency SCA/FI Protection
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Hardware Accelerator for SHA-2 and HMAC with Low Latency SCA/FI Protection
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nQrux™ Confidential Computing Engine (CCE)
- Complete physical isolation of code & data
- Secure code & data transmission with TLS 1.3 Quantum-safe crypto option
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Unified Hardware IP for Post-Quantum Cryptography based on Kyber and Dilithium
- Turn-key implementations of the NIST FIPS recommended CRYSTALS post-quantum for key encapsulation (KEM) and digital signature algorithm (DSA)
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Poly1305 core
- Processing of a 128-bit dataword in as low as 4 clock cycles
- Different processing architectures offering different balances between throughput/area
- Fixed time processing for resistance against timing attacks
- Simple register-based interface
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Combined ChaCha20 and Poly1305 core
- Multiple processing modes:
- Chacha20 processing of 64-bytes in as low as 13 clock cycles
- Poly1305 processing of 16-bytes in as low as 4 clock cycles
- Different processing architectures offering different balances between throughput/area
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ChaCha20 stream cipher core
- Simple register based interface
- Processing of 64-bytes in as low as 13 clock cycles
- Selection between High Throughput or Low Gate-Count architectures
- Real-time selection between key generation or cipher/decipher modes
