Poly1305 core

Overview

Key Features

• Processing of a 128-bit dataword in as low as 4 clock cycles
• Different processing architectures offering different balances between throughput/area
• Fixed time processing for resistance against timing attacks
• Simple register-based interface
• Split clock domains allow power reduction by using the AHB clock domain for configuration, with a local system-clock domain to perform processing
• AMBA 3 AHB slave interface for configuration
• Optional support for interfacing with DMA-engine for greater throughput
• Verilog 2001

Benefits

• Easy integration into Arm or other microprocessor SoC
• Small size and high performance

Block Diagram

Applications

• Transport Layer Security (TLS)
• OpenSSH
• IPsec
• Ultra-low power embedded web-servers

Deliverables

• RTL
• Testbench
• Software libraries

Technical Specifications