SerDes PMA IP
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63
IP
from 16 vendors
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10)
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Multiprotocol SerDes PMA
- Supports over 30 protocols including CEI 6G & 11G SR, MR, LR, Ethernet 10GBASE-X/S/K/R, PCIe Gen1/2/3/4, V-by-One HS/US, CPRI, PON, OTN/OTU, 3GSDI, JESD204A/B/C, SATA1-3, XAUI, SGMII
- Programmable (De)Serialization width: 8, 10, 16, 20, 32, or 40 bit
- Tx ring PLL includes fractional multiplication, spread spectrum and Jitter Cleaner function for Sync-E and OTU
- Core-voltage line driver with programmable pre-and post-emphasis
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25/28/32G Combo SerDes
- 4 Channels per Quad
- Data rate up to 25/28/32Gbps
- Shared Quad LC-PLL for high performance
- Independent Ring-PLL of each channel for clock flexibility
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Programmable PCIe2/SATA3 SERDES PHY on TSMC CLN28HPC
- Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
- Compact form factor – 0.116 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 6.3 mW/Gbps (@6Gbps) including termination
- Minimal latency – 3 UI between parallel transfer and serial transmission
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Programmable Low Power SERDES Receiver on TSMC CLN65LP
- Programmable SERDES analog receiver that supports 0.6 to 3.75 Gbps standard serial protocols
- Compact form factor – 0.1 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 6.8 mW/Gbps including termination
- Minimal latency – 4 UI between parallel transfer and serial transmission
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Programmable Low Power SERDES on TSMC CLN40G
- Programmable SERDES analog front end that supports 1 to 11+ Gbps standard serial protocols
- Compact form factor – 0.104 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 5.8 mW/Gbps including termination
- Minimal latency – 3 UI between parallel transfer and serial transmission
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Programmable Low Power SERDES on TSMC CLN28HPL
- Programmable SERDES analog front end that supports 1 to 6+ Gbps standard serial protocols
- Compact form factor – 0.095 mm2 active silicon area per lane including ESD
- Industry leading low power – typically 5.6 mW/Gbps including termination
- Minimal latency – 3 UI between parallel transfer and serial transmission
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PCIe Express Gen4 / Ethernet SERDES on TSMC CLN5A
- Industry leading low power PMA macro – 122.9mW per lane at 16Gbps (7.7mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Support for Ethernet protocols and Automotive Grade 2
- Compact form factor – 0.34 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
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PCI Express Gen5 SERDES PHY on Samsung 8LPP
- Industry leading low power PMA macro – 224mW per lane at 28Gbps (8.0 mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.38 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
- Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
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PCI Express Gen4 SERDES PHY on Samsung 7LPP
- Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Compact form factor – 0.32 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission
- Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
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PCI Express Gen4 / Ethernet SERDES on TSMC CLN5
- Industry leading low power PMA macro – 122.9mW per lane at 16Gbps (7.7mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
- Support for Ethernet protocols and Automotive Grade 2
- Compact form factor – 0.34 mm2 active silicon area per lane including ESD
- Minimal latency – 3 UI between parallel transfer and serial transmission