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Samsung Foundry 14LPP IP

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Compare 17 IP from 5 vendors (1 - 10)
  • 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
    • The 1.8V capable GPIO is an IP macro for on-chip integration. It is a 1.8V general purpose I/O built with a stack of 1.2V MOS FINFET devices. It is controlled by 0.75V (core) signals.
    • Supported features include core isolation, output enable and pull enable. Extra features such as input enable/disable, programmable drive strength and pull select, can be supported upon request.
    Block Diagram -- 1.8V Capable GPIO on Samsung Foundry 4nm FinFET
  • HSSTP TX PHY 5nm Samsung Foundry
    • Samsung Foundry 5nm (SF5A) CMOS device technology
    • 1.8V±5%, 0.75V±5% power supply
    • Fully supports ARM HSSTP v6.0
    • Supports 1.5/3/6Gbps data rates
    Block Diagram -- HSSTP TX PHY 5nm Samsung Foundry
  • USB 3.0 PHY - Samsung 28LPP18 x1, OTG, North/South (vertical) poly orientation
    • Part of a comprehensive IP solution including xHCI host and device controllers, PHYs, verification IP, IP Prototyping Kits and IP software development kits
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
    • USB-C femtoPHY IP supports USB Type-C specification
    Block Diagram -- USB 3.0 PHY - Samsung 28LPP18 x1, OTG, North/South (vertical) poly orientation
  • Ultra Low Power Embedded SRAM - Samsung 28FDSOI
    • Single port, single voltage rail synchronous SRAM
    • Hierarchical Bit Line – subdividing the array into columns/ rows, banks and local blocks.
    • Configurable mux factor sets column length and overall aspect ratio
    • Bit Line Voltage control eliminates potential low operating voltages issues
    Block Diagram -- Ultra Low Power Embedded SRAM - Samsung 28FDSOI
  • USB 3.0 PHY in Samsung (28nm, 14nm)
    • Complete mixed-signal physical layer for USB 3.0 applications
    • Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
    • USB-C 3.0 femtoPHY supports Type-C reversible connectors
    • Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
  • USB 3.0 femtoPHY in Samsung (14nm, 11nm, 10nm)
    • Complete mixed-signal physical layer for USB 3.0 applications
    • Includes all circuitry needed for operation at all USB speeds (SuperSpeed, High-Speed, FullSpeed, Low-Speed)
    • USB-C 3.0 femtoPHY supports Type-C reversible connectors
    • Optimized PHY area (<0.5mm2 for USB 3.0, <0.8mm2 for USB-C 3.0)
  • USB 2.0 femtoPHY in Samsung (14nm, 11nm, 8nm, 7nm, 5nm, SF4X)
    • Designed for advanced 1.8V CMOS planar bulk and FinFET process nodes
  • MIPI D-PHY TRx 28nm
    • Samsung Foundry 5nm low power enhanced (LN28LPP) CMOS device technology
    • 1.8V±5%, 1.2V±5%,1V±5% power supply
    • Fully supports MIPI D-PHY v1.2 HS/LP/ULPS Tx/Rx (Backward Compatible with previous versions)
    • Supports 80-2100Mbps in D-PHY HS mode
    Block Diagram -- MIPI D-PHY TRx 28nm
  • MIPI D-PHY TRx 5nm
    • Samsung Foundry 5nm low power enhanced (LN11LPP) CMOS device technology
    • 1.8V±5%, 1.2V±5%, 0.8/0.9V±5% power supply
    Block Diagram -- MIPI D-PHY TRx 5nm
  • MIPI D-PHY TRx 14nm
    • Samsung Foundry 5nm low power enhanced (LN14LPP/LPU) CMOS device technology
    • 1.8V±5%, 1.2V±5%, 0.8/0.9V±5% power supply
    • Fully supports MIPI D-PHY v1.2 HS/LP/ULPS Tx/Rx (Backward Compatible with previous versions)
    • Supports 80-2100Mbps in D-PHY HS mode
    Block Diagram -- MIPI D-PHY TRx 14nm
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