SM4 IP
Filter
Compare
38
IP
from
10
vendors
(1
-
10)
-
Security Protocol Accelerator for SM3 and SM4 Ciphers
- Highly customer configurable, silicon-proven security accelerator
- Support for Chinese security SM3 and SM4 (modes: ECB, CTR, CBC, CCM, GCM, XTS) algorithms
- Option: Differential Power Analysis (DPA) countermeasures for SM4
- Built-in scatter/gather DMA capability offloads the host processor
-
SM4 Encoder and Decoder
- Compliant with GBT.32907-2016
- Support both encryption and decryption
- Support ECB, CBC and multiple ciphering modes
-
Tunable SM4 Hardware accelerator with SCA protections
- AMBA interface
- Supported key sizes: 128 bits
- Multiple modes supported: ECB, CBC, CFB, OFB, CTR, CMAC, CCM, GMAC, GCM, XTS
- Compliant with GM/T 0002-2012 and GBT.32907-2016
-
SM4 Cipher Engine
- The SM4 IP core implements a custom hardware accelerator for the SM4 symmetric block cipher, specified in Chinese national standard GB/T 32907-2016, and ISO/IEC 18033-3:2010/Amd 1:2021.
- Designed for easy integration, the core, internally expanding the 128-bit key, is capable of both encryption and decryption and features a simple handshake input and output data interface.
-
SM4-GCM Multi-Booster crypto engine
- ASIC & FPGA
- High throughput
- Guaranteed performance with small packets
-
SM4-XTS Multi-Booster
- ASIC and FPGA
- High throughput
- Scalable solution
-
Fast Inline Cipher Engine, AES-XTS/GCM, SM4-XTS/GCM, DPA
- One input word per clock without any backpressure
- Design can switch stream, algorithm, mode, key and/or direction every clock cycle
- GCM: throughput is solely determined by the data width, data alignment and clock frequency
- XTS: block processing rate may be limited by the number of configured tweak encryption & CTS cores; a configuration allowing 1 block/clock is available
-
Cryptographic engine using the DES, Triple-DES or AES
- The cryptographic processor (CRYP) can be used both to encrypt and decrypt data using the DES, Triple-DES, AES or SM4 algorithms.
-
RVA23, Multi-cluster, Hypervisor and Android
- 64-bit out-of-order 4 wide decode 13-stage CPU core with 128 reordering buffers and 8 functional pipelines
- Symmetric multiprocessing up to 8 cores
- Private L2 cache support
- Level-3 shared cache and coherence support
