RapidIO 4.1 Controller IP
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SD 4.1 Hardware Validation Platform
- Designed to be cost-effective and Linux based, this SD 4.1 hardware validation platform (HVP) consists of Arasan’s SD4.0 IP mapped into FPGA’s, offering full speed physical connectivity to a complementary SoC host or memory card device.
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UHS-II PHY Core IP
- The UHS-II PHY IP is a comprehensive, silicon-proven configurable core that has been ported to multiple process nodes and leading foundries.
- It uses sub-LVDS signaling consisting of one pair each for transmit, receive, and an additional reference clock. This low-pin interface has reduced power consumption and low EMI.
- To further reduce power, the reference clock operates at 1/15 or 1/30 of the data transfer speed.
