RISC-V Tensor unit IP
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RISC-V Tensor Unit
- Ultra-Fast AI
- 64-bit Core Integration
- Vector Unit and Gazzillion Integration
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High Bandwidth Out-of-Order RISC-V IP Core
- 64-bit Core
- Vector Ready
- Multiprocessor Ready
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High Bandwidth In-Order RISC-V IP Core
- Decodes 2 instructions/cycle
- In-order issue
- Gazzillion Misses™
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Highly scalable inference NPU IP for next-gen AI applications
- Matrix Multiplication: 4096 MACs/cycles (int 8), 1024 MACs/cycles (int 16)
- Vector processor: RISC-V with RVV 1.0
- Custom instructions for softmax and local storage access
