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PCIe PHY IP

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Compare 472 IP from 40 vendors (1 - 10)
  • PCI Express 4.0 PHY
    • Compiles with PCIe 4.0, 3.1, 2.1, 1.1 and PIPE 4.4.1 Specifications
    • Supports all power saving modes (P0, P0s, P1, P2) as defined in PIPE 4.4.1 spec.
    Block Diagram -- PCI Express 4.0 PHY
  • PCIe 4.0 PHY on 5nm
    • Low power consumption and small area
    • Support 1-, 2- and 4- lane configurations
    • Automatic built-in self-test (Loopback)
    Block Diagram -- PCIe 4.0 PHY on 5nm
  • PCIe 6.0 PHY on 5nm
    • Low power consumption and small area
    • Support 1-, 2- and 4- lane configurations
    • Automatic built-in self-test (Loopback)
    Block Diagram -- PCIe 6.0 PHY on 5nm
  • PCIe 4.0 PHY on 8nm
    • Low power consumption and small area
    • Support 1-, 2- and 4- lane configurations
    • Automatic built-in self-test (Loopback)
    Block Diagram -- PCIe 4.0 PHY on 8nm
  • Compute Express Link (CXL) 1.1/2.0/3.0 Controller
    • Implements CXL 3.0 Specification at 64 GT/s
    • Parallel Multiple TLP/DLLP processing engine for best performance, throughput, and latency
    • Designed for easy integration with PipeCORE™ PCIe® PHY IP
    Block Diagram -- Compute Express Link (CXL) 1.1/2.0/3.0 Controller
  • IP for Automotive Applications
    • M31 M-PHY certified by ISO 26262 ASIL-B is a serial interface technology which is widely adopted in automotive devices interface transmission. As a MIPI Alliance contributor and an Interface IP provider, M31 provides a silicon-proven, low-power and low cost M-PHY IP in different process nodes.
    • M31 D-PHY certified by ISO 26262 ASIL-B Ready is a very popular physical layer interface for mobile applications as it is a flexible, high-speed, low-power and low-cost solution. M31 also provides silicon-proven D-PHY in various process nodes. Many car and mobile devices manufacturers are adopting MIPI specifications because the solutions are mature, relatively simple to use.
    • M31 PCIe PHY certified by ISO 26262 ASIL-B Ready provides high-performance, multi-lane capability and low power architecture for the high-bandwidth applications. It is optimized the minimal die area and low power consumption. The safe mechanism of PCIe PHY is compliant with PCI Express Base 4.0, PCI Express Base 3.1, PCI Express Base 2.1 and PCI Express Base It can meet the complete range of PCIe high bandwidth application in different channel conditions.
    • M31 High Speed Memory Compilers including “One-Port”, “Two-Port”, “Single-Port”, and “Dual-Port” have all passed ISO 26262 ASIL-B Ready and ASIL-D Ready certification. High speed SRAM instances are the fundamental blocks for all automotive applications. Users can generate different memory types, sizes and configurations according to different requirements. In addition, the compilers provide customers comprehensive product applications with vehicle safety requirements. Furthermore, the whole series products are ASIL D Ready certified and provide optimized IP portfolio solutions for different customer’ designs with more flexible choices of design architecture.
  • PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
    • Fully compliant with PCI Express Base 5.0 electrical specifications
    • Compliant with PIPE5.2 (PCIe) specification
    • Supports all power-saving modes (P0, P0s, P1, and P2) defined in PIPE4.4.1 spec
    Block Diagram -- PCIe 5.0 PHY IP for Storage and High-Bandwidth Connection
  • PCIe Gen2 PHY
    • PCI Express Gen 2 and Gen 1 compliant
    • Supports various PCI Express modes and extensions
    • Programmable amplitude and pre-emphasis
    • Programmable receiver equalization
    Block Diagram -- PCIe Gen2 PHY
  • PCIe Gen3 PHY
    • Low Risk - Silicon proven with Si characterization data
    • Excellent Interoperability
    • Superior Noise Immunity
    Block Diagram -- PCIe Gen3 PHY
  • High Performance, Low Latency PCIe Gen5 PHY
    • 8 lane PCIe 32/16/8/5/2.5 Gbps per lane
    • Tight skew control of less than 1UI between lanes of the PMA
    Block Diagram -- High Performance, Low Latency PCIe Gen5 PHY
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