PCIe Gen1-5 PHY TSMC 7nm IP
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PCIe Gen5 PHY, x2-lane, RC/EP, TSMC 12FFC, N/S orientation
- Fully compliant with PCI Express Base 5.0 electrical specification
- Compliant with PIPE5.2 (PCIe) specification
- Supports all power saving modes (P0, P0s, P1, P2) defined in the PIPE5.2 specification
- Supports L1 PM Substates with CLKREQ#
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PCIe 5.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
- Compliant with PCIe 5.0 Base Specification
- Compliant with PIPE 5.1
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s, 16.0 GT/s and 32GT/s
- Supported physical lane width: x4
