IP Catalog > PCIe 4.0 SerDes PHY

PCIe 4.0 SerDes PHY IP

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Compare 21 IP from 8 vendors (1 - 10)
  • PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
    • Compliant with PCIe 4.0 Base Specification
    • Compliant with PIPE 4.4
    • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
    • Supported physical lane width: x4
    Block Diagram -- PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
  • PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm
    • Compliant with PCIe 4.0 Base Specification
    • Compliant with PIPE 4.4
    • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
    • Supported physical lane width: x4
    Block Diagram -- PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm
  • PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
    • Compliant with PCIe 4.0 Base Specification
    • Compliant with PIPE 4.4
    • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
    • Supported physical lane width: x4
    Block Diagram -- PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
  • PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
    • Compliant with PCIe 4.0 Base Specification
    • Compliant with PIPE 4.4
    • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
    • Supported physical lane width: x4
    Block Diagram -- PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
  • PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
    • Compliant with PCIe 4.0 Base Specification
    • Compliant with PIPE 4.4
    • Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
    • Supported physical lane width: x4
    Block Diagram -- PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
  • PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
    • Wide range of protocols that support networking, high-performance computing (HPC), and applications
    • Low-latency, long-reach, and low-power modes
    • Multi-Link PHY—mix protocols within the same macro
    • EyeSurf —non-destructive on-chip oscilloscope
    • User-friendly graphical interface provides easy access to embedded bit-error-rate (BER) and pattern testers and monitors to measure the link performance in real time
    Block Diagram -- PHY for PCIe 4.0 - Low-power, long-reach, multi-protocol PHY for PCIe 4.0
  • PCI Express Gen4 SERDES PHY on Samsung 7LPP
    • Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.32 mm2 active silicon area per lane including ESD
    • Minimal latency – 3 UI between parallel transfer and serial transmission
    • Single-lane macro scalable to unlimited link width – x1, x2, x4, x8, x16, etc.
  • PCI Express Gen3/4 Enterprise Class SERDES PHY on Samsung 14LPP
    • Industry leading low power PMA macro – 132.7mW per lane at 16Gbps (8.4mW/Gbps) inclusive of Tx and Rx PLLs, termination, bias, etc.
    • Compact form factor – 0.266 mm2 active silicon area per lane including ESD
    • Enterprise class Long Reach 5-tap DFE supporting beyond standard PCIe Channels
    • Minimal latency – 3 UI between parallel transfer and serial transmission
  • 16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
    • Support PCIe G1 to G4 with PCS soft-macro supporting PIPE 4.4.1
    • Support xPON applications: Sym/Asym GPON, Sym/Asym 10GPON, Sym EPON, Sym/Asym 10GEPON
    Block Diagram -- 16Gbps multi-protocol programmable SerDes PHY in UMC 28HPC+
  • 32G LR Multi-Protocol SerDes (MPS) PHY - GLOBALFOUNDRIES 22nm
    • Supports data rates of 2.5 to 32 Gbps
    • Optimized for low-power operation and north/south die-edge placement
    • AC-coupled RX front end with on-chip capacitors
    • Flexible ASIC interface for sharing impedance codes among multiple PMA hard macros and reducing the number of external reference resistors for impedance calibration
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