Overview
Faraday 16Gbps multi-protocol programmable SerDes PHY IP in UMC 28HPC+ process is designed with a system-level approach to provide optimization of power, performance and area to meet the growing needs for high bandwidth and low latency in the applications of consumer, access layer networking device to core/enterprise layer.
The silicon verified 16Gbps SerDes PHY supports the optimization of SoC chip designs to enable the infrastructure of 10G/40G Ethernet, PCIe 4.0, 5G, and most xPON applications. Compared with the other latest Serdes solutions, it is the only solution that supports both PCIe 4.0 and 10G xPON ONU/OLT in 28nm node.
This full-duplex, high-performance and many-protocols compatible SerDes solution comes with a scalable PMA which can be applied to a wide range of applications across copper and backplane channels with total insertion loss more than 30dB. It is also compatible with standard PCS and controller, and provides flexible design environment for users to customize PCS and controller integration.
Provider
Faraday Technology
HQ:
Taiwan
Faraday Technology Corporation is a leading fabless ASIC and silicon IP provider. The company's broad silicon IP portfolio includes I/O, Cell Library, Memory Compiler, ARM-compliant CPUs, DDRI/II/III, MPEG4, H.264, USB 2.0/3.0, 10/100 Ethernet, Serial ATA, and PCI Express, etc. Headquartered in Taiwan, Faraday has service and support offices around the world, including the U.S., Japan, Europe, and China. Faraday is listed in Taipei Stock Exchange, ticker 3035.
Learn more about Multi-Protocol PHY IP core
Morgan State University (MSU) recently received an Apple Innovation Grant, designed to support engineering schools as they develop their silicon and hardware technologies. The New Silicon Initiative (NSI) is designed to inspire and prepare students for careers in hardware engineering, computer architecture, and silicon chip design.
Increasingly, more of the focus on mobile has centered around cloud datacenters and the networking to get the data back and forth between these datacenters and the mobile device. Functions like voice recognition and mapping depend on the ability to split the functionality between the smartphone, for local processing like encryption and compression, and the back end, where a large number of servers can do the heavier lifting before returning the results.
Steven Brown
The Cadence 10G multi-protocol PHY was architected to address this exact challenge. Designed to scale across multiple process nodes, it consolidates PCI Express (PCIe), USB, DisplayPort, Ethernet, and other interfaces into a single, compact, silicon-efficient block. What sets it apart is simultaneous multi-protocol support, which enables multiple data paths without duplicating hardware, requiring extra board connectors, or paying the area and power penalty of separate IP blocks.
