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PCIe 4.0 PHY IP

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Compare 282 IP from 18 vendors (1 - 10)
  • PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC16FFC x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC16FFC x1, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC N7+ x4, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC N7+ x4, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC N7 x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC N7 x1, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC 28HPCP x4, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC 28HPCP x2, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC 28HPCP x2, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC 16FFPGL x8, North/South (vertical) poly orientation
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