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PCIe 4.0 IP

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Compare 563 IP from 34 vendors (1 - 10)
  • PCIe 4.0 Controller
    • PCIe Controller is a high performance PCIE controller, it can support PCIE 1.0/2.0/3.0/4.0 protocol, and the support speed is 2.5G/5G/8G/16G.
    • PCIe Controller support dual mode (ROOT mode or Endpoint mode).
    • PCIe Controller’s interface with PHY is PIPE 4.0 interface and the PCIe Controller’s interface with application layer is the AXI4.0 interface, and it also has a APB bus for register access.
    • The Lane number is configable, it can support X1, X2, X4 lanes.
  • PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC7FF x4, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC7FF x2, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC16FFC x4, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC16FFC x2, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC16FFC x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC16FFC x1, North/South (vertical) poly orientation
  • PCIe 4.0 LP PHY, TSMC N7RF x1, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 LP PHY, TSMC N7RF x1, North/South (vertical) poly orientation
  • PCIe 4.0 PHY, TSMC N7+ x4, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 PHY, TSMC N7+ x4, North/South (vertical) poly orientation
  • PCIe 4.0 LP PHY, TSMC N7 x4, North/South (vertical) poly orientation
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 LP PHY, TSMC N7 x4, North/South (vertical) poly orientation
  • PCIe 4.0 LP PHY, TSMC N7 x2, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
    • Compliant with the PCI Express (PCIe®) 4.0, 3.1, 2.1, 1.1, and PIPE specifications
    • x1, x2, x4, x8, x16 lane configurations with bifurcation
    • Multi-tap adaptive and programmable Continuous Time Linear Equalizer (CTLE) and Decision Feedback Equalization (DFE)
    • Supports lane margining at the receiver
    Block Diagram -- PCIe 4.0 LP PHY, TSMC N7 x2, North/South (vertical) poly orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
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