PCIe 4.0 IP
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344
IP
from 22 vendors
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10)
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PCIe 4.0 Controller with AMBA AXI interface
- Complies with the PCI Express Base 4.0 Specification,
- Supports Endpoint and rootport configuration
- Supports x16, x8, x4, x2, x1 at Gen4, Gen3, Gen2, Gen1 speeds
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PCIe 4.0 Controller supporting Endpoint, Root Port, Switch, Bridge and advanced features
- Complies with the PCI Express Base 4.0 Specification, Rev 4.0
- Supports Endpoint, Root-Port, Dual-mode, Switch
- Supports link rate of 2.5, 5.0, 8.0 and 16.0 Gbps per lane.
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PCIe 4.0 PHY on 5nm
- Low power consumption and small area
- Support 1-, 2- and 4- lane configurations
- Automatic built-in self-test (Loopback)
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PCIe 4.0 PHY on 8nm
- Low power consumption and small area
- Support 1-, 2- and 4- lane configurations
- Automatic built-in self-test (Loopback)
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PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 16FFC
- Compliant with PCIe 4.0 Base Specification
- Compliant with PIPE 4.4
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
- Supported physical lane width: x4
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PCIe 4.0 Serdes PHY IP Silicon Proven in TSMC 7nm
- Compliant with PCIe 4.0 Base Specification
- Compliant with PIPE 4.4
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
- Supported physical lane width: x4
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PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 28HPCP
- Compliant with PCIe 4.0 Base Specification
- Compliant with PIPE 4.4
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
- Supported physical lane width: x4
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PCIe 4.0 Serdes PHY IP, Silicon Proven in UMC 28HPC
- Compliant with PCIe 4.0 Base Specification
- Compliant with PIPE 4.4
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
- Supported physical lane width: x4
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PCIe 4.0 Serdes PHY IP, Silicon Proven in TSMC 12FFC
- Compliant with PCIe 4.0 Base Specification
- Compliant with PIPE 4.4
- Supported data transfer rate: 2.5 GT/s, 5.0 GT/s, 8.0 GT/s and 16.0 GT/s
- Supported physical lane width: x4
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PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)
- Physical Coding Sublayer (PCS) block with PIPE interface
- Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
- Lane margining at the receiver
- Spread-spectrum clocking (SRIS)