PCI Express 3.0 PHY IP
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47
IP
from 8 vendors
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10)
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PCIe 3.0, 2.1, 1.1 Controller with the PHY Interface for PCI Express (PIPE) specification and native user interface support
- Complies with the PCI Express® Base 3.0 Specification, rev.3.1
- Supports Endpoint, Root-Port, Dual-Role, Switch configurations
- Supports x16, x8, x4, x2, x1 at Gen3, Gen2, Gen1 speeds
- Implements one Virtual Channel
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Samsung 28nm FDSOI USB3.0 and PCIE2 combo PHY
- USB3.0 Super-Speed: Universal Serial Bus 3.0 Specification, Revision 1.0
- PCI Express: PCI Express Base Specification, Revision 2.0
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PCIe 3.0, 2.1, 1.1 Controller supporting Root Port, Endpoint, Dual-mode Configurations, with AMBA AXI User Interface
- PCIe Interface
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PCIe Gen1/2 PHY
- Fully compliant with PCI-SIG’s PCIe v2.0 specification.
- PHY package includes configurable PIPE interface (8 bit/ 16 bit/ 32bit). User can choose the interface width as per the application requirement.
- Generates whole range of Ordered Sets as required by PCIe 2.0 Specification with synchronized LTSSM.
- IBM implementation compatible 8b/10b Encoder and Decoder.
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Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 65G process
- - Quad PCIe 8/5/2.5 Gbps per lane
- - Tight skew control of less than 1UI between lanes of the PMA
- - Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
- - Lowest latency
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Single Lane and Quad Lane 8Gbps PCIe3.0 PHY in Samsung 28LPP process
- Single Lane and Quad Lane
- Samsung 28LPP process
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Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in GF 28SLP process
- - Quad PCIe 8/5/2.5 Gbps per lane
- - Tight skew control of less than 1UI between lanes of the PMA
- - Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
- - Lowest latency
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Single Lane and Quad Lane 8Gbps PCIe3.0 PHY IP in TSMC 28HPC process
- - Quad PCIe 8/5/2.5 Gbps per lane
- - Tight skew control of less than 1UI between lanes of the PMA
- - Multi-tap Tx Finite Impulse Response (FIR) equalizer with multi-level de-emphasis
- - Lowest latency
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PCIe 3.0 PHY IP
- Physical coding sublayer (PCS) block with PIPE interface
- PCIe 3.0 PHY with backward compatibility
- Spread-spectrum clocking (SRIS)
- Supports L0-L2 power states and L1.1 and L1.2 substates
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PCIe 5.0 Customizable Embedded Multi-port Switch
- 1 Upstream port
- Multiple Downstream ports (2 up to 32)
- x1, x2, x4, x8 PCI Express Core
