IP Catalog > PCI Express® 4.0

PCI Express® 4.0 IP

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Search (36)
Compare 36 IP from 2 vendors (1 - 10)
  • Configurable controllers for PCIe 4.0 and CCIX supporting Dual Mode applications
    • Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
    • Full Transaction Layer, Data Link Layer and Physical Layer
    • Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
    • Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
  • PCIe 4.0 PHY in Samsung (14nm, 11nm, SF5A, SF2)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SRIS)
  • PCIe 4.0 LP PHY in TSMC (N7) for Automotive
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SRIS)
  • PCIe 4.0 PHY in GF (14nm, 12nm)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SRIS)
  • PCIe 4.0 LP PHY in
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SRIS)
  • Configurable controllers for PCIe 4.0 supporting Endpoint, Root Complex, Switch Port, and Dual Mode applications
    • Available in all port types including: Endpoint, Embedded Endpoint, Root Complex, Switch Port, Bridge, Dual Mode (Endpoint/Root Complex), and Multi-Port Switch
    • Full Transaction Layer, Data Link Layer and Physical Layer
    • Supports up to sixteen 64.0, 32.0, 16.0, 8.0, 5.0, 2.5 GT/s lanes
    • Available in 32-, 64-, 128-, 256-, 512- or 1024-bit datapath widths for maximum flexibility
  • PCIe 4.0 PHY in TSMC (28nm, 16nm, 12nm, N7, N3P)
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SRIS)
  • PCIe 4.0 PHY in
    • Physical Coding Sublayer (PCS) block with PIPE interface
    • Support PCIe 4.0, 3.1, 2.1, 1.1 encoding, backchannel initialization
    • Lane margining at the receiver
    • Spread-spectrum clocking (SRIS)
  • 10Gbps Multi-Link and Multi-Protocol PCIe 4.0 PHY IP for SMIC
    • Supports USB 3.1, PCIe 3.0/2.0/1.0, DP-TX v1.4/ eDP-TX v1.4b, SATA 3, QSGMII,and SGMII
    • Supports PCIe L1 sub-states
    • Supports SRIS and internal SSC generation
    • Multi-protocol support for simultaneous independent links
  • PCIe 2.0 PHY in GF (40nm, 28nm, 22nm, 12nm)
    • Physical coding sublayer (PCS) block with PIPE interface
    • Supports PCIe power management features, including L1 substate
    • Power gating for lowest standby power
    • Low active power using voltage mode TX with under drive supply options
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