OTP TSMC N5A IP
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30
IP
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10)
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64x1 Bits OTP (One-Time Programmable) IP, TSMC 0.18um SiGe BiCMOS 1.8V/3.3V General Purpose Process
- Fully compatible with TSMC 0.18um SiGe BiCMOS 1.8V/3.3V General Purpose process
- Wide operating voltage range:
- – Read voltage: 1.8 V ± 10% VDD and VDDP
- – Program Voltage: 2.7-3.63 V VDDP and 1.8 V ± 10% VDD
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16x8 Bits OTP (One-Time Programmable) IP, TSMC CM018G 0.18um 1.8V/3.3V Process
- Compatible with TSMC CM018G 0.18um 1.8V/3.3V process
- Core 1.8 V devices only
- Wide voltage range: 1.4–2.0 V read voltage and 3.3 V ± 5% program voltage.
- Speed: program time 9–30 µs per bit, 500-ns read cycle time, 8-bit at a time
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4Kx8 Bits OTP (One-Time Programmable) IP, TSMC 0.18µm 1.8V/5V Mixed-Signal Process
- Fully compatible with TSMC 0.18µm mixed-signal process
- Low voltage: 1.8 V ± 10% read and 3.6 V ± 5% program
- High speed: 10-µs program time per bit, and 30-ns cycle time to read 8 bits at a time
- Asynchronous input and latched output
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32x8 Bits OTP (One-Time Programmable) IP, TSMC 0.18um Mixed-Signal 1.8V/3.3V Process
- Fully compatible with TSMC 0.18um 1.8V/3.3V Mixed-Signal, General Purpose process
- Wide voltage range: 1.05-3.6 V read voltage and 3.6-3.9 V program voltage
- Speed: 9-15.3 µs program time per bit, & 1000-ns read cycle time (1 MHz, max.), 8-bit outputs at a time
- Asynchronous mode with output latches
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768x39 Bits OTP (One-Time Programmable) IP, TSMC 55ULP 0.9V–1.2V / 2.5V Process
- Fully compatible with standard TSMC 55nm ULP 0.9–1.2V / 2.5V CMOS process
- Low voltage: VDD 0.85–1.32 V read and VDDP 1.77 V ± 5% program
- High speed program: 10-us single-bit programming
- High speed read: 5-Mhz read clock (200-ns cycle time) at 39-bit word.
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4608x12 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 0.9V/2.5V Process
- Fully compatible with standard TSMC 40nm ULP 0.9V/2.5V CMOS logic process
- Low voltage: VDD 0.9 V ± 10% for read and program; VDDP: 1.71–3.60 V for read and 2.65 V ± 5% for program
- High speed program: 10-us programming time and support up to dual-bit concurrent programming at one CLK cycle
- High speed read: 10-MHz read clock (100-ns cycle time) per 12-bit word.
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1Kx8 Bits OTP (One-Time Programmable) IP, TSMC 40ULP 1.1/2.5V Process
- Fully compatible with standard TSMC 40nm ULP 1.1V / 2.5V CMOS process
- Low voltage: VDD 1.1 V ± 10% read and VDDP 2.1 V ± 5% program
- High speed program: 10-us single-bit programming
- High speed read: 9-MHz read clock at 8-bit word.
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256x16 Bits OTP (One-Time Programmable) IP, TSMC 152nm 1.8V/3.3V GP MS Process
- Fully compatible with standard TSMC 1P6M 152nm GP MS CMOS core logic process
- Low program voltage: 3.8+/-0.1V VDDP andVDDP2, and 0.8-1.32V VDD
- Low read voltage: 1.35-1.55V VDDP and VDDP2 and 0.8-1.32V VDD
- High speed: 10us program time per bit
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128x8 Bits OTP (One-Time Programmable) IP, TSMC 55nm LP 1.2V/2.5V & ULP 0.9V/2.5V Mixed-Signal, General Purpose Process
- Fully compatible with TSMC 55nm LP 1.2V*/2.5V & ULP 0.9V*/2.5V CMOS process
- Wide voltage range: 0.81 V (0.9 V-10%)–1.32 V (1.2 V+10%) read voltage and 2.5 V± 5% program voltage
- High speed: 10-µs program time per bit, & 100-ns read cycle time (10 Mhz, max.), 8-bit at a time
- Ultra-low read energy: <3 pJ per bit