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Neuromorphic Processor IP

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  • Neuromorphic Processor IP (Second Generation)
    • Supports 8-, 4-, and 1-bit weights and activations
    • Programmable Activation Functions
    • Skip Connections
    • Support for Spatio-Temporal and Temporal Event-Based Neural Network
    Block Diagram -- Neuromorphic Processor IP (Second Generation)
  • Neuromorphic Processor IP
    • Supports 4-, 2-, and 1-bit weights and activations
    • Supports multiple layers simultaneously
    • Convolutional Neural Processor (CNP) and
    • Fully-connected Neural Processor (FNP)
    Block Diagram -- Neuromorphic Processor IP
  • Ultra low power inference engine
    • Neuromorphic processor
    • Sub milliwatt power
    • Ultra-low power AI processing
    Block Diagram -- Ultra low power inference engine
  • NASP PPG IP Block
    • Input and output interfaces are adaptable and configurable for any type of digital bus line or analog signal, tailored to customer requirements.
    Block Diagram -- NASP PPG IP Block
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