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NCR Processor IP

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  • NCR Processor
    • NCR (Network Clock Reference) is a procedure to provide the master clock (i.e. time information) of the satellite to all its user terminals.
    • Typically, NCR packets are provided periodically over a continuous DVB-S2 or DVB-S2X link.
    • The receiving user terminal uses the knowledge of the master clock in the system to determine when it is allowed to transmit data in a time-division multiple access (TDMA) system, such as DVB-RCS or DVB-RCS2.
    Block Diagram -- NCR Processor
  • DVB-S2X WideBand Demodulator IP
    • Two high-symbol-rate (HSR) demodulators: Maximum baud rate 500 Msymbol/s, Up to two slices each,DVB-S2/S2X and Annex M compliant
    • Up to 8 multi-standard demodulators: S/S2/S2X/DTV
    • Integrated full-band tuners and ADCs
    • High-speed digital multiplexer to connect any tuner to any demodulator
    Block Diagram -- DVB-S2X WideBand Demodulator IP
  • DVB-S2X WideBand Demodulator & Decoder IP (Silicon Proven)
    • Two high-symbol-rate (HSR) demodulators : Maximum baud rate 500 Msymbol/s,Up to two slices each, DVB-S2/S2X and Annex M compliant
    • Up to 8 multi-standard demodulators:S/S2/S2X/DTV
    • Integrated full-band tuners and ADCs
    • High-speed digital multiplexer to connect any tuner to any demodulator
    Block Diagram -- DVB-S2X WideBand Demodulator & Decoder IP (Silicon Proven)
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Semiconductor IP