MIPI RFFE v2.0 IP

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Compare 3 IP from 2 vendors (1 - 3)
  • Simulation VIP for MIPI RFFE
    • Topology
    • Multiple subordinate and multiple main devices topology
    • Packet Generation
    • Command, Address, Data, and No Response Frame generation
    Block Diagram -- Simulation VIP for MIPI RFFE
  • RFFE Slave IP Core
    • Compliant with MIPI’s RFFE specification Rev 3.0
    • Small silicon footprint
    • Scalable Implementation
    • Up to 15 Devices can be connected per Bus
    • Low pin count on Interface side (SCLK and SDATA)
    Block Diagram -- RFFE Slave IP Core
  • RFFE Master IP Core
    • Compliant with MIPI RFFE Specification 3.0
    • Delivered in Reuse Methodology Manual (RMM) compliant Verilog RTL format
    • Optionally delivered as a physical design
    • Small footprint
    Block Diagram -- RFFE Master IP Core
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Semiconductor IP