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MIPI D-PHY IP

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Compare 589 IP from 36 vendors (1 - 10)
  • MIPI D-PHY Verification IP
    • Compliant to MIPI D-PHY Specification Version 3.5 with PPI interface.
    • Support HS-IDLE State between two data burst.
    • Support for Alternate calibration Sequence & Preamble sequence.
    • Supports all possible configuration for Data Lane Module and Clock Lane Module at PHY layer.
    Block Diagram -- MIPI D-PHY Verification IP
  • Simulation VIP for MIPI D-PHY, C-PHY and A-PHY
    • PHY Monitor
    • Built-in scoreboarding between serial/PPI interface, also monitors error signal interface
    • Reports any detected error on any lane on serial interface and is not reflected on PPI interface
    • C-PHY and D-PHY
    Block Diagram -- Simulation VIP for MIPI D-PHY, C-PHY and A-PHY
  • MIPI D-PHY
    • Physical interface for CSI-2 and DSI providing 2.5Gbps per lane of bandwidth
    • MIPI D-PHY Analog Transceiver IP Core is fully compliant to the D-PHY specification version 1.1.
    • It supports the MIPI® Camera Serial Interface (CSI-2) and Display Serial Interface (DSI) protocols. It is a Universal PHY that can be configured as a transmitter, receiver, or transceiver.
  • MIPI DPHY Verification IP
    • Full MIPI DPHY Transmitter and Receiver functionality.
    • Supports 3.0 MIPI DPHY Specifications.
    • Supports both serial and PPI functionality testing.
    • Supports short and long packets
    Block Diagram -- MIPI DPHY Verification IP
  • MIPI D-PHY Verification IP
    • Compliant to MIPI D-PHY Specification Version 3.5 with PPI interface.
    • Support HS-IDLE State between two data burst.
    • Support for Alternate calibration Sequence & Preamble sequence.
    • Supports all possible configuration for Data Lane Module and Clock Lane Module at PHY layer.
    Block Diagram -- MIPI D-PHY Verification IP
  • MIPI D-PHY Universal IP in UMC 28HPC+
    • Supports MIPI Alliance Specification for D-PHY Version 2.5
    • Consists of 1 Clock lane and 4 Data lanes
    • Embedded, high performance, and highly programmable PLL
    • Supports both low-power mode and high speed mode with integrated SERDES
    Block Diagram -- MIPI D-PHY Universal IP in UMC 28HPC+
  • MIPI D-PHY TX PHY and DSI controller
    • Scalability and Flexibility: Supports multiple data lanes for higher aggregate bandwidth, any of the multiple lanes can be configured into Clock Lane
    • High Data Rates: Supports data transmission rates up to 4.5Gbps per lane, allowing for high-resolution displays and smooth refresh rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Solution: Combines the MIPI D-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
    Block Diagram -- MIPI D-PHY TX PHY and DSI controller
  • MIPI D-PHY TX & RX + DSI & CSI Controllers
    • Compliant with MIPI Committee Specifications
    • High Data Rates: Supports data transmission rates up to 4.5Gbps per lane, allowing for high-resolution displays and smooth refresh rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Display Solution: Combines the MIPI D-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
  • MIPI DPHY v1.2 TX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v1.2
    • Fully integrated hard macro
    • Up to 2.5 Gbps per lane
    • Aggregate throughput up to 10 Gbps in 4 data lanes
    Block Diagram -- MIPI DPHY v1.2 TX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
  • MIPI DPHY v1.2 RX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
    • Compliant with the MIPI D-PHY specification, v1.2
    • Fully integrated hard macro
    • Up to 2.5 Gbps per lane
    • Aggregate throughput up to 10 Gbps in 4 data lanes
    Block Diagram -- MIPI DPHY v1.2 RX 4 Lanes - UMC 28HPC 1.8V, North/South Poly Orientation
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