MIPI D-PHY IP
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393
IP
from 32 vendors
(1
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10)
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MIPI D-PHY / C-PHY Combo IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for C-PHY specification Version 1.2
- Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
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MIPI D-PHY IP for TSMC (5nm, 6/7nm, 12/16nm, 22nm, 28nm, 40nm)
- Compliant to MIPI Alliance Standard for D-PHY specification Version 2.1, 1.2, 1.1
- Supports standard PHY transceiver compliant to MIPI Specification
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
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MIPI D-PHY Tx IP, Silicon Proven in TSMC 22ULP
- DSI PCS :
- The Register Bank is accessible through a standard AMBA-APB slave interface, providing access to the DSI PHY registers for configuration and control.
- Host_adapter: remapping PPI Signal with lane control and phy_adapter block;
- Lane_ctrl block (clklane_ctrl/datalane0_ctrl/datalane1_ctrl/datalane2_ctrl/datalane3_ctrl)
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MIPI D-PHY IP 4.5Gbps in TSMC N7
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 4 Data lanes
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MIPI D-PHY CSI-2 TX (Transmitter) in TSMC 28HPC+
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 2 Data lanes
- Embedded, high performance, and highly programmable PLL
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MIPI D-PHY Rx IP, Silicon Proven in TSMC 28HPC+
- Compliant to MIPI Alliance Standard for
- D-PHY specification Version 1.2
- Supports standard PPI interface compliant to MIPI Specification
- Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
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MIPI D-PHY Universal IP - 4.5Gbps/lane, MIPI D-PHY v2.5 Compliant in TSMC 22ULP
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Backward compatible with MIPI Specifications for D-PHY v2.1, v1.2, and v1.1
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MIPI D-PHY CSI-2 TX+ (Transmitter) IP in TSMC 22ULL
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 4 Data lanes
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MIPI D-PHY CSI-2 RX (Receiver) in Samsung 28FDSOI
- Consists of 1 Clock lane and up to 4 Data lanes
- MIPI DPHY V1.1 specifications
- Supports both high speed and low-power modes
- 80 Mbps to 1.5 Gbps data rate in high speed mode
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MIPI D-PHY Universal IP in TSMC 28HPC+
- Supports MIPI Alliance Specification for D-PHY Version 2.5
- Consists of 1 Clock lane and 4 Data lanes
- Embedded, high performance, and highly programmable PLL
