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MIPI D PHY IP

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Search (13)
Compare 13 IP from 8 vendors (1 - 10)
  • MIPI C/D Combo TX PHY and DSI controller
    • High Data Rates: Supports data transmission rates
    • Energy Efficiency: Optimized for low power consumption, making it ideal for battery-powered devices
    • Complete Solution: Combines the MIPI CD-PHY Transmitter PHY and DSI Controller to make it a one-stop solution
    • Flexible IP Configuration


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    Block Diagram -- MIPI C/D Combo TX PHY and DSI controller
  • MIPI DSI-2 Transmitter IIP
    • Compliant with MIPI DSI-2 Specification v1.3
    • Compliant with D - PHY Specification v1.1,v1.2,v2.0,v2.1
    • Compliant with C - PHY Specification v0.7,v1.2
    • Compliant with Display Pixel Interface (DPI -2) v 2.0
    Block Diagram -- MIPI DSI-2 Transmitter IIP
  • MIPI DSI-2 Receiver IIP
    • Compliant with MIPI DSI-2 specification v1.3
    • Compliant with D - PHY Specification v1.1,v1.2,v2.0,v2.1
    • Compliant with C - PHY Specification v0.7,v1.2
    • Compliant with Display Pixel Interface (DPI -2) v 2.0
    Block Diagram -- MIPI DSI-2 Receiver IIP
  • MIPI CSI-2 Transmitter IIP
    • Compliant with MIPI CSI-2 Specification v1.0, v1.1, v1.3, v2.0,v2.1
    • Compliant with D - PHY Specification v1.1,v1.2,v2.0,v2.1
    • Compliant with C - PHY Specification v0.7,v1.2,v2.0
    • Full MIPI CSI-2 TRANSMITTER functionality where either D - PHY / C - PHY can be used
    Block Diagram -- MIPI CSI-2 Transmitter IIP
  • MIPI CSI-2 Receiver IIP
    • Compliant with MIPI CSI-2 Specification v1.0, v1.1, v1.3, v2.0,v2.1
    • Compliant with D - PHY Specification v1.1,v1.2,v2.0,v2.1
    • Compliant with C - PHY Specification v0.7,v1.2,v2.0
    • Full MIPI CSI-2 RX functionality where either D - PHY / C - PHY can be used
    Block Diagram -- MIPI CSI-2 Receiver IIP
  • MIPI D-PHY Tx IP, Silicon Proven in TSMC 40LP
    • Compliant to MIPI Alliance Standard for
    • D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high speed mode with a bit rate of 80-2500 Mb/s
    Block Diagram -- MIPI D-PHY Tx IP, Silicon Proven in TSMC 40LP
  • MIPI DSI DisplayTransmitter IP
    • MIPI DSI Transmitter IP is designed to transmit the data to the host processor
    • The MIPI DSI-2 provides the mobile industry a standard, robust, scalable, low-power, high-speed, cost-effective interface that supports a wide range of imaging solutions for mobile devices
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    Block Diagram -- MIPI DSI DisplayTransmitter IP
  • MIPI D-PHY Tx IP, Silicon Proven in SMIC 55LL
    • Compliant to MIPI Alliance Standard for D-PHY specification Version 1.2
    • Supports standard PPI interface compliant to MIPI Specification
    • Supports synchronous transfer at high-speed mode with a bit rate of 80-2500 Mb/s
    • Supports asynchronous transfer at low power mode with a bit rate of 10 Mb/s
    Block Diagram -- MIPI D-PHY Tx IP, Silicon Proven in SMIC 55LL
  • MIPI UniPro Stack - v1.6
    • MIPI UniPro Compliant
    • Type I for M-PHY
    • MIPI M-PHY Version 3.0
    • Multi-lane: one to four
  • CSI2 TX; Camera Serial Interface, MIPI Compliant
    • Supports up to 4-Data lanes
    • Supports up to 4-virtual channels
    • The Data lanes can be programmed to operate either at 1 or 2 or 3 or 4 lanes
    • Each Data lane supports up to 1.5Gbps at High Speed mode and up to 10 Mbps at Low power mode
    Block Diagram -- CSI2 TX; Camera Serial Interface, MIPI Compliant
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