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LCD TFT display controller IP

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  • RGB to CCIR 601 / 656 Encoder
    • The DB1892 performs the following video signal processing functions:
    • Color Space Converter - Inputs RGB 24-bit data and sync signals VSYNC, HSYNC, & Date Enable from a LCD Controller. The Color Space Converter converts the 4:4:4 sampled RGB pixels to component luma and chroma digital video 4:4:4 YCbCr.
    • Chroma Resampler - The Chroma Resampler down converts the 4:4:4 YCbCr to 4:2:2 YCbCr, in order to meet the ITU-R BT.601 requirements of the ITURBT. 656 Encoder.
    • BT.656 Encoder - Encodes the 4:2:2 YCbCr component digital video with synch signals to conform to the ITU-RBT.656 digital coding standard.
  • AHB TFT LCD Controller
    • 24-bit TFT LCD Controller
    • 16 x 32-Pixel FIFO
    • 256-Pixel Palette Mode
    • True Color and 24-bit Color support
    Block Diagram -- AHB TFT LCD Controller
  • Display Controller - LCD / OLED Panels (AHB Bus)
    • Wide range of programmable Display Panel resolutions:
    • Releases supporting baseline display requirements and advanced releases with following optional display processing features:
    • Overlay Windows option comes with advanced composition features:
    • Color Palette RAM per layer or single Palette for integrated display image
  • Display Controller - LCD / OLED Panels (AHB-Lite Bus)
    • Wide range of programmable LCD Panel resolutions:
    • Support for 1 Port TFT LCD Panel interfaces:
    • Programmable frame buffer bits-per-pixel (bpp) color depths:
    • Programmable Output format support:
    Block Diagram -- Display Controller - LCD / OLED Panels (AHB-Lite Bus)
  • Display Controller - LCD 4K Digital Cinema (DCI)
    • Support for following LCD Panel resolutions:
    • 3840 x 2160 Quad / Ultra Full High Definition (QFHD)
    • 4096 x 2160 Digital Cinema Systems (DCI)
    • 2048 x 1080 Digital Cinema Systems (DCI)
    Block Diagram -- Display Controller - LCD 4K Digital Cinema (DCI)
  • Multilayer Configurable Display Controller
    • Fully programmable clock and timing control for flat panel displays with progressive scanning
    • Support for resolutions up to 4096x4096
    • Completely variable timing parameters, for standard or specific display resolutions
    • Support for 8,16, 18 or 24 bit RGB output color depth
    Block Diagram -- Multilayer Configurable Display Controller
  • Lightweight Configurable Display Controller
    • Fully programmable clock and timing control for flat panel displays with progressive scanning
    • Support for resolutions up to 4096×4096
    • Completely variable timing parametersfor standard or specific display resolutions
    • Support for 8,1618 or 24 bit RGB output color depth
    Block Diagram -- Lightweight Configurable Display Controller
  • 2D Graphics Hardware Accelerator (AXI4 Bus)
    • Bit Block Transfer - 3 Independent Memory Sources of data
    • .2D Raster Operations (ROP) performed on Block Transfers
    Block Diagram -- 2D Graphics Hardware Accelerator (AXI4 Bus)
  • BitBLT Graphics Hardware Accelerator (AHB Bus)
    • Bit Block Transfer – 3 Independent Memory Sources of data:
    • 2D Raster Operations (ROP) performed on Block Transfers:
    • BitBLT Draw Features:
    • 2D Graphics Rendering Engine (Option):
    Block Diagram -- BitBLT Graphics Hardware Accelerator (AHB Bus)
  • BitBLT Graphics Hardware Accelerator (AXI Bus)
    • Bit Block Transfer – 3 Independent Memory Sources of data:
    • 2D Raster Operations (ROP) performed on Block Transfers:
    • BitBLT Draw Features:
    • 2D Graphics Rendering Engine (Option):
    Block Diagram -- BitBLT Graphics Hardware Accelerator (AXI Bus)
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