ISO 26262 ASIL B IP

• ARM® Cortex®-R5 and Cortex-R7 processor port checking
• Hardware duplication and redundancy
• Custom ECC and parity generation and checking

32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification

• 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications

• Supports multiple coherent agents, including Armv9 and RISC-V CPU clusters
• AMBA CHI-E, CHI-B and ACE interoperability, as well as ACE-Lite and AXI
• Low-latency proxy caches for efficient and quick integration of hardware accelerators into the coherent domain
• Configurable last-level caches

• Standalone IP
• 1.2 GHz frequency in 16FF+TT process
• Protocol interoperability: AMBA AXI 4

• Scales from 10s to 100s of IP blocks
• Automatically generates ring, mesh and torus networks
• View and edit generated topologies

• ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
• ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
• Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

• Compliant with the latest MIPI C-PHY and D-PHY specifications
• Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
• D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
• C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes

• Compliant with the latest MIPI C-PHY and D-PHY specifications
• Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
• D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
• C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes

• Compliant with the latest MIPI C-PHY and D-PHY specifications
• Fully verified IP available in TX, RX, or master and slave configuration, including all analog and digital circuitry
• D-PHY mode includes a clock lane and two or four data lanes, each supporting a maximum of 6.5Gb/s per lane in high- speed modes
• C-PHY mode includes two or three trios, each supporting a maximum of 6.5Gs/s per trio in high-speed modes