Codasip L31AS is a 32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification. Part of our safety and security offering, this embedded processor is ideal either as a Main Controller or a Safety Island in a Functional Safety System.
It includes 2 instances of Codasip L31 in a dual-core lockstep configuration along with Physical Memory Protection as a security feature.
32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification
Overview
Key Features
- Core
- In-order, 3-stage, single-issue pipeline
- RV32IMC ISA
- Memory protection
- Physical memory attributes with 16 regions
- Interrupts
- WFI and NMI
- PIC
- Interfaces
- Separate Data and Instruction AHB-Lite Interfaces
- Power & Performance
- Block-level gating in single-core configuration.
- Performance Counters
- Debug
- Standard RISC-V debug
- 4 debug triggers
- Debug Memory Interface (DMI) as an APB interface that can be used to interface with external debuggers.
- System bus access
- Safety Mechanism
- State of Art, Dual Core Lock Step (DCLS), with clock offset setting
- Safety Pack
- Safety Manual
- Safety Case Report
- Certification
- TÜV Süd ISO 26262 ASIL B
Block Diagram
Technical Specifications
Foundry, Node
Any
Availability
Now
Related IPs
- ARC Functional Safety (FS) Processor IP supports ASIL B and ASIL D safety levels to simplify safety-critical automotive SoC development and accelerate ISO 26262 qualification
- 32-bit CPU IP core supporting ISO 26262 ASIL B level functional safety for automotive applications
- FlexNoC Functional Safety (FuSa) Option helps meet up to ISO 26262 ASIL B and D requirements against random hardware faults.
- Ultra High Performance 32-bit RISC-V Embedded Processor
- 32-bit Embedded RISC-V Functional Safety Processor
- RISC-V CPU IP With ISO 26262 Full Compliance