Dma controller IP

The MC-SDMA IP core implements a highly configurable, bandwidth-efficient, and easy-to-use Direct Memory Access (DMA) controller that transfers data between the host system’s memory and multiple peripherals equipped with streaming interfaces.
The core interfaces with the host memory via a manager AMBA^® AXI4 (memory-mapped) port and provides access to its configuration and status registers (CSRs) via a subordinate AXI4-Lite or APB4 interface.

The memory 2 memory DMA controller transfers data from one memory location to another memory location.
DMA operation begins when software enables a DMA, after setting the source and destination starting addresses, transfer count, and control information.
The DMA engine moves the data block, and the DMA operation ends naturally when the number of bytes specified by the transfer count has been moved

The AXI4-SGDMA IP core implements a Host-to-Peripheral (H2P), or a Peripheral-to-Host (P2H) Direct Memory Access (DMA) engine, which interfaces the host system with an AXI4 Memory-Mapped master port and the peripheral with either a slave or a master AXI4-Stream port.
The core operates in either Scatter-Gather (SG) Mode, reading descriptors from a run-time defined memory mapped-location, or in Direct Mode, transferring data according to a descriptor stored in local registers.

Supports 1-16 channel DMA Transmit and DMA Receive Engine
Supports latest ARM AMBA 3/4 AXI, AXI4-Lite, AMBA4 ACE, AMBA4 ACE-Lite, AXI4-Stream specification.
Supports access for Ring and Chained Descriptor Structures
Configurable Transmit and Receive Engine based on Host Memory Data Width

The ULL PCIe DMA Controller is a high-performance, bidirectional data transfer solution. It is designed for seamless communication between FPGAs and host CPUs over PCIe.
With a round-trip time as low as 585ns*, this IP core empowers developers to maximize resource utilization and achieve ultra-low latency without compromising performance.

DMA Controller IP