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Compare 3,350 IP from 147 vendors (1 - 10)
  • 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
    • A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V to 5V GPIO, 1.8V to 5V analog, with ultra low-cap/low-leakage RF solutions.
    • This silicon proven flip-chip compatible library in TSMC 180nm BCD features a multi-voltage GPIO, 1.8V to 5V analog I/O, and ultra-low capacitance and low leakage 36V+ ESD solutions. The library also includes 5V RF pads.
    Block Diagram -- 1.8V to 5V GPIO, 1.8V to 5V Analog in TSMC 180nm BCD
  • Specialed 20V Analog I/O in TSMC 55nm
    • A TSMC 55nm LP Specialized 20V Analog I/O in Standard Low Voltage CMOS
    • This silicon-proven TSMC 55nm LP 20V ESD cell is a high-voltage electrostatic discharge (ESD) protection solution specifically engineered forlow-power and high-performance applications.
    • This ESD cellis designed to safeguard high- voltage interfaces commonly found in analog, mixed-signal, RF, and power management ICs, where protection against electrostatic discharge events is critical for long-term reliability.
  • 1.8V GPIO, 1.8V to 3.3V Analog in TSMC 180nm BCD
    • A Flip-Chip compatible I/O Library in TSMC 180nm BCD with 1.8V GPIO, 1.8V to 3.3V Analog, with ultra low-cap/low-leakage 36V+ ESD solutions.
    • This silicon proven flip-chip compatible library in TSMC 180nm BCD features a 1.8V GPIO, 1.8 to 3.3V analog I/O, and ultralow capacitance and low leakage 36V+ ESD solutions.
    Block Diagram -- 1.8V GPIO, 1.8V to 3.3V Analog in TSMC 180nm BCD
  • 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
    • A Flipchip I/O Library with dynamitcally switchable 1.8V/3.3V GPIO, 5V I2C/SM- Bus ODIO, 5V OTP Cell, 1.8V & 3.3V Analog Cells and associated ESD.
    • A key attribute of this library is its ability to detect and dynamically adjust to a VDDIO supply of 1.8V or 3.3V during system operation.
    Block Diagram -- 1.8V/3.3V I/O Library with 5V ODIO & Analog in TSMC 16nm
  • Wirebond Digital and Analog Library in TSMC 65nm
    • A mixed Digital and Analog Library, compatible with I2C and I3C Protocols.
    • This library is a mixed Digital and Analog library built for the TSMC 65nm process.
    • It is based around a Fail-Safe General Purpose Input/Output (FSGPIO) cell that is compatible with both I2C and I3C protocols.
    Block Diagram -- Wirebond Digital and Analog Library in TSMC 65nm
  • Wide Range Programmable Integer PLL on UMC L65LL
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Fully integrated inside customer-specified IO ring
    Block Diagram -- Wide Range Programmable Integer PLL on UMC L65LL
  • Wide Range Programmable Integer PLL on UMC L130EHS
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture using core logic devices only
    • Fully integrated inside industry standard’s IO ring with proprietary low noise ESD structure
  • Wide Range Programmable Integer PLL on TSMC CLN90G-GT-LP
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Fully integrated inside customer-specified IO ring
  • Wide Range Programmable Integer PLL on TSMC CLN80GC
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Fully integrated inside customer-specified IO ring
    Block Diagram -- Wide Range Programmable Integer PLL on TSMC CLN80GC
  • Wide Range Programmable Integer PLL on TSMC CLN7FF
    • Electrically Programmable PLL for multiple applications
    • Wide Ranges of Input and Output Frequency for diverse clocking needs
    • Implemented with Analog Bits’ proprietary architecture
    • Low power consumption
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