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Search (10,093)
Compare 10,093 IP from 391 vendors (1 - 10)
  • UCIe IP
    • Supporting x16 link width with speeds up to 16 GT/s per lane, it conforms to UCIe’s standardized interface for seamless chiplet integration.
    • Developed on GlobalFoundries 12LP+, this IP includes custom PHY, protocol, and die-to-die layers—engineered for performance, flexibility, and low latency.
  • HBM4 PHY IP
    • Supports JEDEC HBM4 DRAMs
    • Supports data rates up to 12 Gbps
    • Supports up to 32 independent 64-bit memory channels
    • Pseudo-channel operation supported to enable up to 64 32-bit pseudo-channels with 2048-bit PHY
  • HBM4 Controller IP
    • Supports JEDEC standard HB4 DRAM
    • DFI 5.1 compliant interface to HBM4 PHY
    • Multiport Arm® AMBA® interface (AXI™) with managed QoS per pseudo-channel or single-port host interface(HIF), per channel 
    • Data rate support 12 Gbps or higher
  • 3.6Kbit EEPROM IP with configuration 28p8w16bit
    • 130GF_EEPROM_08 IP is a nonvolatile electrically erasable programmable read-only memory (EEPROM) with volume 3.6 Kbits, which is organized as 28 pages of 8 words by 16 bit with single-bit output data and parallel write data.
    • Data programming in EEPROM consists of 2 consecutive phases - erasing and writing.
    Block Diagram -- 3.6Kbit EEPROM IP with configuration 28p8w16bit
  • SLVS-EC RX PHY IP
    • Fully compliant with SLVS-EC v3.0 specification.
    • Supports both synchronous and asynchronous clocking.
    • Up to 10Gbps per lane with 40-bit parallel data bus.
    • Maximum output clock frequency of 250MHz.
  • Ethernet PHY IP
    • Compliant to 802.3 Ethernet specification - 200GBASE-KR4, 200GBASE-CR4, 100GBASE-KR4, 100GBASE-CR4, 100GBASE-KR2, 100GBASE-CR2, 50GBASE-KR, 50GBASE-CR, 40GBASE-KR4, 40GBASE-CR4, 25GBASE-KR, 25GBASE-CR, 10GBASE-KR, 10GBASE-CR
    • Data rate supported - Ethernet: NRZ 3.125 - 26.5625Gb/s, PAM4 53.125Gb/s
    • DSP-based architecture using high-performance ADC/DAC for RX/TX
    Block Diagram -- Ethernet PHY IP
  • 1G BASE-T Ethernet Verification IP
    • The 1G BASE-T Ethernet Verification IP provides deliverables an effective & efficient way to verify the components interfacing with the Ethernet interface of an IP or SoC. 
    •  The 1G Ethernet VIP is fully compliant with the IEEE standard 802.3 specification.
    • This VIP is lightweight with easy plug -and- play interface so that there is no hit on the design cycle time.
    Block Diagram -- 1G BASE-T Ethernet Verification IP
  • eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
    • RapidFlex eFPGA IP provides a reconfigurable, upgradeable, and iterative logic computing layer for SoCs, MCUs, AI accelerators, industrial control, and communication chips.
    • Based on RapidFlex's self-developed ArkAngel® toolchain (AAEE), our eFPGA core delivers full-flow capabilities from architecture exploration → RTL → physical implementation (GDSII) → digital design flow verification, leading the industry in performance density, integrability, and toolchain experience.
    Block Diagram -- eFPGA IP — Flexible Reconfigurable Logic Acceleration Core
  • UCIe PHY (Die-to-Die) IP
    • Compliant with UCIe v2.0, supporting 4/8/12/16/24/32GT/s data rates
    • for Standard Package up to 16 lanes / for Advanced Package up to 64 lanes
    • Provides a 1024-bit data bus width with high-throughput die-to-die communication
    • Includes automatic per-lane calibration and optional transmitter de-emphasis
    Block Diagram -- UCIe PHY (Die-to-Die) IP
  • UA Link TL IP core
    • UALink_200 Specifi cation Compliant: Implements TL functions per Rev 1.0
    • Multi-Rate Support : 200 GBASE-KR1/CR1, 400 GBASE-KR2/CR2, 800 GBASE-KR4/CR4
    • Atomic Operations, Authentication tags, Cache Synchronization, Flow Control
    Block Diagram -- UA Link TL IP core
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Semiconductor IP