ASIL-ready certified IP
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209
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ASIL-B Ready PUF Hardware Premium with key wrap and certification support
- Synopsys AP PUF is a physical unclonable function (PUF)-based RoT component that can be applied easily to almost any MCU/SoC/ASIC and is fab and process agnostic.
- This IP has been developed following an ISO 26262 functional-safety-compliant flow and meets the ISO 26262 Automotive Safety Integrity Level (ASIL) B fault metric.
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ASIL-B Ready PUF Hardware Base
- Synopsys AP PUF is a physical unclonable function (PUF)-based RoT component that can be applied easily to almost any MCU/SoC/ASIC and is fab and process agnostic.
- This IP has been developed following an ISO 26262 functional-safety-compliant flow and meets the ISO 26262 Automotive Safety Integrity Level (ASIL) B fault metric.
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MIPI DSI-2 V2 Host Controller ASIL Compliant
- Compliant with the MIPI DSI and DSI-2 specifications, v2.1
- Support for dual MIPI DSI use case with VESA Display Stream Compression (DSC) v1.1 standard
- Support for video and command modes
- Wide PPI interface to C-PHY v1.2 and D-PHY v2.1
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MIPI D-PHY Tx 2 Lanes - TSMC N7 1.8V, North/South Poly Orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI D-PHY Rx 4 Lanes - TSMC 7FF18, North/South Poly Orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI D-PHY Tx 4 Lanes - TSMC 16FFC18, North/South Poly Orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI D-PHY Rx 4 Lanes - TSMC 16FFC18, North/South Poly Orientation for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY v1.2 RX 2 Lanes - TSMC 16FFC 1.8V, North/South Poly Orientation for Automotive ASIL B Random, AEC-Q100 Grade 2
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY v1.2 TX 2 Lanes - TSMC 16FFC 1.8V, N/S, for Automotive, ASIL B Random, AEC-Q100 Grade 2
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
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MIPI DPHY v1.2 TX 4 Lanes - SS 8LPU 1.8V, North/South Poly Orientation for Automotive ASIL B Random, AEC-Q100 Grade 1
- Compliant with the MIPI D-PHY specification, v1.2
- Fully integrated hard macro
- Up to 2.5 Gbps per lane
- Aggregate throughput up to 10 Gbps in 4 data lanes
