ASIL IP

• ARM® Cortex®-R5 and Cortex-R7 processor port checking
• Hardware duplication and redundancy
• Custom ECC and parity generation and checking

32-bit RISC-V embedded processor with TÜV SÜD ISO 26262 ASIL B certification

• 32-bit CPU IP core that supports ISO 26262 ASIL B level functional safety for automotive applications

• ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
• ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
• Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.

• Industry’s only USB Type-C IP solution consisting of USB-C 3.1/DisplayPort 1.3 Tx PHYs, USB-C 3.1/DisplayPort 1.3 Tx controllers with HDCP 2.2 and HDCP 1.4 content protection, verification IP, IP subsystems, IP prototyping kits, and IP software development kits
• Solution supports USB Type-C, SuperSpeed USB 3.1 at 10 Gbps, SuperSpeed USB 3.0 at 5 Gbps and High-Speed USB (USB 2.0) as well as DisplayPort 1.3 Tx supporting RBR, HBR1, HBR2 and HBR3 bitrates
• Controllers support Device, Host, and Dual-Role Device USB-C 3.1 as well as DisplayPort 1.3 Tx with HDCP 2.2 content protection

• Supports data rates up to 40Gb/s and bandwidth density of 12.9Tbps/mm
• Compliant with the latest UCIe specification
• Integrated signal integrity monitors and comprehensive test and repair features
• Supports high-density advanced packaging technologies such as silicon interposer, silicon bridge, and RDL fanout

• Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
• Support for data rates up to 4,267 Mbps (process dependent)
• Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
• PHY independent, firmware-based training using an embedded calibration processor

• Supports JEDEC standard LPDDR4X, LPDDR4, LPDDR3, DDR4, DDR3, and DDR3L (1.35V DDR3) SDRAMs
• Support for data rates up to 4,267 Mbps (process dependent)
• Designed for rapid integration with Synopsys Enhanced Universal DDR Memory/Protocol Controllers (uMCTL2/uPCTL2) for a complete DDR interface solution
• PHY independent, firmware-based training using an embedded calibration processor

• Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
• Support for data rates up to 6400 Mbps
• Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
• DFI 5.0 controller interface

• Supports JEDEC standard LPDDR5X, LPDDR5, LPDDR4 and LPDDR4X SDRAMs
• Support for data rates up to 6400 Mbps
• Designed for rapid integration with Synopsys’ LPDDR5/4/4X controller for a complete DDR interface solution
• DFI 5.0 controller interface