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ARC EV6x Embedded Vision Processor IP

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Compare 164 IP from 8 vendors (1 - 10)
  • ARC EV Processors are fully programmable and configurable IP cores that are optimized for embedded vision applications
    • ARC processor cores are optimized to deliver the best performance/power/area (PPA) efficiency in the industry for embedded SoCs. Designed from the start for power-sensitive embedded applications, ARC processors implement a Harvard architecture for higher performance through simultaneous instruction and data memory access, and a high-speed scalar pipeline for maximum power efficiency. The 32-bit RISC engine offers a mixed 16-bit/32-bit instruction set for greater code density in embedded systems.
    • ARC's high degree of configurability and instruction set architecture (ISA) extensibility contribute to its best-in-class PPA efficiency. Designers have the ability to add or omit hardware features to optimize the core's PPA for their target application - no wasted gates. ARC users also have the ability to add their own custom instructions and hardware accelerators to the core, as well as tightly couple memory and peripherals, enabling dramatic improvements in performance and power-efficiency at both the processor and system levels.
    • Complete and proven commercial and open source tool chains, optimized for ARC processors, give SoC designers the development environment they need to efficiently develop ARC-based systems that meet all of their PPA targets.
  • ARC SEM110 Security Processor for Low Power Embedded Applications
    • Performance-, power- and area-efficient security processors for embedded applications
    • Secure privilege mode orthogonal to kernel/user mode
    • Enhanced secure MPU with context ID for secure or normal operation
    • Up to 16 configurable protected regions and per region scrambling capability
    Block Diagram -- ARC SEM110 Security Processor for Low Power Embedded Applications
  • ARC EM6 32-bit processor core with cache for embedded applications
    • Very small size - 0.01mm2 (28 HPM)
    • 1.81 DMIPS/MHz performance, 4.18 CoreMarks/MHz
    • Up to 240 interrupts with 16 levels
    • 512B - 2MB instruction closely coupled memory (ICCM)
    Block Diagram -- ARC EM6 32-bit processor core with cache for embedded applications
  • ARC EM4 32-bit processor core, ARC V2 ISA, for embedded applications
    • Very small size - 0.01mm2 (28 HPM)
    • 1.81 DMIPS/MHz performance, 4.18 CoreMarks/MHz
    • Up to 240 interrupts with 16 levels
    • 512B - 2MB instruction closely coupled memory (ICCM)
    Block Diagram -- ARC EM4 32-bit processor core, ARC V2 ISA, for embedded applications
  • ARC HS36 32-bit processor core, ARC V2 ISA, for embedded applications
    • Achieves up to 3232 DMIPS and 6681 CoreMarks* at 1.61 GHz on 28HPM (single-core configuration, worst case silicon and conditions)
    • Delivers 2.13 DMIPS/MHz, 4.15 CoreMarks/MHz* (per core)
    • High-speed, 10-stage pipeline
    • Up to 16MB instruction and data close coupled memory (CCM)
    Block Diagram -- ARC HS36 32-bit processor core, ARC V2 ISA, for embedded applications
  • ARC HS34 32-bit processor core, ARC V2 ISA, for embedded applications
    • Achieves up to 3232 DMIPS and 6681 CoreMarks* at 1.61 GHz on 28HPM (single-core configuration, worst case silicon and conditions)
    • Delivers 2.13 DMIPS/MHz, 4.15 CoreMarks/MHz* (per core)
    • High-speed, 10-stage pipeline
    • Up to 16MB instruction and data close coupled memory (CCM)
    Block Diagram -- ARC HS34 32-bit processor core, ARC V2 ISA, for embedded applications
  • ARC HS46 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications
    • Dual-issue, 32-bit processor for high-performance embedded applications
    • Deliver up to 5700 DMIPS and 9880 CoreMark per core at 1.9 GHz on 16ff (worst case conditions, single-core configuration)
    • 3.0 DMIPS/MHz, 5.2 CoreMarks/ MHz (per core)
    • Based on advanced ARCv2 ISA
    Block Diagram -- ARC HS46 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications
  • ARC HS44 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications
    • Dual-issue, 32-bit processor for high-performance embedded applications
    • Deliver up to 5700 DMIPS and 9880 CoreMark per core at 1.9 GHz on 16ff (worst case conditions, single-core configuration)
    • 3.0 DMIPS/MHz, 5.2 CoreMarks/ MHz (per core)
    • Based on advanced ARCv2 ISA
    Block Diagram -- ARC HS44 32-bit, dual-issue processor core, ARC V2 ISA, for embedded applications
  • ARC HS38 32-bit processor with MMU, ARCv2 ISA, for embedded Linux applications
    • Achieves up to 3232 DMIPS and 6681 CoreMarks* at 1.61 GHz on 28HPM (single-core configuration, worst case silicon and conditions)
    • Delivers 2.13 DMIPS/MHz, 4.15 CoreMarks/MHz* (per core)
    • High-speed, 10-stage pipeline
    • Up to 16MB instruction and data close coupled memory (CCM)
    Block Diagram -- ARC HS38 32-bit processor with MMU, ARCv2 ISA, for embedded Linux applications
  • ARC SEM120D Security Processor with DSP for Low Power Embedded Applications
    • Performance-, power- and area-efficient security processors for embedded applications
    • Secure privilege mode orthogonal to kernel/user mode
    • Enhanced secure MPU with context ID for secure or normal operation
    • Up to 16 configurable protected regions and per region scrambling capability
    Block Diagram -- ARC SEM120D Security Processor with DSP for Low Power Embedded Applications
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