IP Catalog > AMBA AHB PCI Express Bridge

AMBA AHB PCI Express Bridge IP

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  • PCI - AMBA AHB Device/Host Bridge
    • This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. 
    • The bridge supports Host Mode and Device Mode (selected by a dedicated input pin). In Host Mode, the bridge is in charge of PCI bus arbitration and generating the PCI reset signal.
    Block Diagram -- PCI - AMBA AHB Device/Host Bridge
  • PCI to AMBA AHB Host Bridge
    • This PCI Host Bridge IP core enables data transfers between an AMBA® AHB host processor bus system and PCI bus based devices. 
    • The bridge enables higher utilization of the bus’ available bandwidth by prefetching PCI data and buffering AHB data, and allows the host to initiate PCI accesses or to respond to transactions initiated by other PCI devices.
    Block Diagram -- PCI to AMBA AHB Host Bridge
  • AMBA AHB to PCI Host Bridge
    • Fully supports PCI specification 2.1 and 2.2 protocol.
    • Supports AHB bus protocol.
    • Downstream access transfer from AHB bus to PCI bus.
    • Upstream access transfer from PCI bus to AHB bus.
    Block Diagram -- AMBA AHB to PCI Host Bridge
  • AMBA AHB Bus Master
    • Supports AHB bus interface to the ARM CPU.
    • User interface designed for high speed access to any slave devices on the AHB Bus.
    • User specified single or burst data access on the AHB interface and user interface.
    • Handles wait state insertion by any slave devices.
    Block Diagram -- AMBA AHB Bus Master
  • AMBA AHB Bus Slave
    • Supports AHB bus interface to the ARM CPU.
    • User interface designed for high speed access to two sets of on-chip or off-chip modules.
    • Four write buffers to process posted write.
    • Dual read buffers to process CPU read.
    Block Diagram -- AMBA AHB Bus Slave
  • AHB To PCI Wrapper
    • VHDL / Verilog source code provided
    • Compliant with AMBA Specification (Rev 2.0)
    • Compliant with PCI Specification (Rev 2.3)
    • Low cost Architecture with low gate count
  • PCI Master Slave IIP
    • Compliant with PCI version 2.0 Specification
    • Supports 32 bit address and data
    • Supports all types device select delays
    • Supports arbiter which is 100% PCI specification compliant
    Block Diagram -- PCI Master Slave IIP
  • Configurable AMBA bus SoC platform
    • Robust and fully synchronous single-edge clock designs
    • Up to 125 MHz in FPGA and 400 MHz on 0.13 um ASIC technologies
    • Fault-tolerant and SEU-proof version
    • Symmetric Multi-processor support (SMP)
  • 32-bit PCI Bus Master/Target
    • Fully supports PCI specification 2.1 and 2.2 protocol.
    • Designed for ASIC and PLD implementations.
    • Fully static design with edge triggered flip-flops.
    • Efficient back-end interface for different types of user devices.
    Block Diagram -- 32-bit PCI Bus Master/Target
  • DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
    • Performance of Greater than 100MHz (200 DDR)
    • Interfaces to JEDEC Standard DDR SDRAMs
    • Supports DDR SDRAM Data Widths of 16, 32 and 64 Bits
    • Supports up to 8 External Memory Banks
    Block Diagram -- DDR SDRAM Controller - Pipelined for ispXPGA and ORCA4
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