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AES-GCM Crypto Engine IP

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Compare 9 IP from 3 vendors (1 - 9)
  • AES-GCM Ultra-low latency crypto engine
    • High throughput: 64 GB/s (512 Gbps)
    • Ultra-low latency
    • Optional CRC support for data integrity
    • 128-bit and 256-bit key
    • NIST SP 800-38D compliant
    Block Diagram -- AES-GCM Ultra-low latency crypto engine
  • AES-GCM Multi-channel upto 2Tbps Crypto Accelerator
    • EXAMPLE CONFIGURATIONS
    • The SafeXcel-IP-63 has a scalable number of processing pipes and channels. It is available in different configurations, suitable for different applications to meet different gate count and throughput objectives.
    • • EIP-63a-c17-r
    • o single pipe, 17 channels, register based (no memories)
  • GEON™ Secure Boot Hardware Engine
    • GEON-SBoot is an area-efficient, processor-agnostic hardware engine that protects SoC designs from booting with malicious or otherwise insecure code.
    • The security platform employs public-key cryptography (which stores no secret on-chip) to ensure that only unmodified firmware from a trusted source is used by the system.
    Block Diagram -- GEON™ Secure Boot Hardware Engine
  • Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
    • Protocol aware IPsec, SSL, TLS, DTLS, 3GPP and MACsec Packet Engine with virtualization, caches classifier and Look-Aside interface for multi-core application processors
    • 5-10 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, AMBA interface
    • Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP, DPDK, Linux Crypto
    Block Diagram -- Multi-Protocol Engine with Classifier, Look-Aside, 5-10 Gbps
  • Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes
    • High throughput
    • Guaranteed performance with small packets
    • 128-bit and 256-bit key
    Block Diagram -- Secure-IC's Securyzr(TM) AES-GCM Multi-Booster Réduire la liste des FPGA aux noms des gammes
  • Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
    • Protocol aware IPsec, SSL, TLS, DTLS, 3GPP, MACsec packet engine with classifier and in-line interface for multi-core server processors
    • 10-100 Gbps, programmable, maximum CPU offload by classifier, supports new and legacy crypto algorithms, streaming and AMBA interface
    • Supported by Driver development kit, QuickSec IPsec toolkit, Linaro ODP.
    Block Diagram -- Multi-Protocol Engine with Classifier, Inline and Look-Aside, 10-100 Gbps
  • AES-XTS Multi-Booster
    • ASIC and FPGA
    • High throughput:
    • Scalable solution
    • Supports 128-bit & 256-bit key
    Block Diagram -- AES-XTS Multi-Booster
  • AES XTS/GCM Accelerators
    • Wide bus interface
    • Basic AES encrypt and decrypt operations
    • Key sizes: 128, 192 and 256 bits
    • Key scheduling in hardware, allowing key, key size and 
direction changes every 13/15/17 clocks with zero impact 
on throughput
    • Hardware reverse (decrypt) key generation
    Block Diagram -- AES XTS/GCM Accelerators
  • Quantum Safe IPsec Toolkit
    • Quantum Safe IPsec Toolkit (QuickSec Quantum) is first to market, complete IPsec software implementation with Quantum Safe cryptography support.
    • Quantum Safe cryptography is designed to be resistant to quantum computer attacks and is required by any up-to-date security product.
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