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AES XTS IP

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Compare 39 IP from 16 vendors (1 - 10)
  • XTS mode AES Processor
    • Supports high throughput AES XTS mode for data storage applications.
    • Compliant with IEEE 1619-2007and NIST SP800-38E recommendations.
    Block Diagram -- XTS mode AES Processor
  • AES Core XTS
    • Complies with IEEE 1619-2007 and NIST SP800-38E standards
    • Performance selectable to meet or exceed USB 3.0 and SATA 3.0 (6 Gbps), even on low cost FPGA families
    • Low area, implementation of AES-XTS suitable for data storage applications.
    • Based on the NIST validated (Cert #953) AES-G3 implementation of FIPS 197 (November 2001) Advanced Encryption Standard
  • AES Encryption Core with XTS
    • Full Verilog core
    • 128 or 256 bit selectable AES encryption
    • The AES-XTS algorithm is FIPS-197 certified, cert. no 2408.
    • The encode and decode channels are made to look and act like independent FIFOs for ease of integration. The control block has a register interface to be easily managed by a hardware state machine or controlled by a processor for operations such as key initialization, and TWEAK configuration and management.
  • Secure-IC's Securyzr™ Tunable AES (ECB, CBC, CTR, XTS, CCM, GCM) accelerator - optional SCA protection
    • AMBA interface
    • Supported key sizes: 128, 192 and 256 bits
    • Multiple modes supported: ECB, CBC, CFB, OFB, CTR, CMAC, CCM, GMAC, GCM, XTS
    • Compliant with NIST SP 800-38
  • AES XTS/GCM Accelerators
    • Wide bus interface
    • Basic AES encrypt and decrypt operations
    • Key sizes: 128, 192 and 256 bits
    • Key scheduling in hardware, allowing key, key size and 
direction changes every 13/15/17 clocks with zero impact 
on throughput
    • Hardware reverse (decrypt) key generation
    Block Diagram -- AES XTS/GCM Accelerators
  • AES supporting ECB, CBC and XTS/XEX modes. Includes DMA and AXI interface.
    • 100% AES compatible
    • >2.4 GB/sec max throughput
    • Up to 8 engines in parallel (configurable)
    • Supports ECB, CBC and XTS/XEX modes
    • Supports BitLocker acceleration
    • Supports Encryption and Decryption
    Block Diagram -- AES supporting ECB, CBC and XTS/XEX modes. Includes DMA and AXI interface.
  • Cryptographic co-processor for lightweight cryptography
    • Support AES-XTS mode — IEEE Std 1619-2007 standard compliance
    • Support 128 and 256-bit key size
    • Random memory block access support
  • DPA- and FIA-resistant Ultra High Bandwidth FortiCrypt AES IP core
    • Ultra-high bandwidth due to multi-pipeline architecture, HUNDREDs Gbps (@500 MHz on a 45nm tech. process)
    • Extensible pipeline architecture
    Block Diagram -- DPA- and FIA-resistant Ultra High Bandwidth FortiCrypt AES IP core
  • Advanced DPA- and FIA-resistant FortiCrypt AES SW library
    • Ultra-strong side-channel and SIFA protection at high performance
    • NIST FIPS-197 compliant
    • AES-128/192/256 encryption and decryption
    • Tunable protection level
    Block Diagram -- Advanced DPA- and FIA-resistant FortiCrypt AES SW library
  • AES Authenticated Encryption Accelerator with DPA or with DPA and FIA
    • The SCA-resistant AES-IP-3X family of crypto accelerator cores provide semiconductor manufacturers with superior AES cipher acceleration.
    • The cores are easily integrated into ASIC/SoC and FPGA devices and offer a high-level of resistance to various Side Channel Attacks like Differential Power Analysis (DPA), and optionally offer detection of Fault Injection Attacks (FIA).
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