AES XTS IP
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XTS mode AES Processor
- Supports high throughput AES XTS mode for data storage applications.
- Compliant with IEEE 1619-2007and NIST SP800-38E recommendations.
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AES Core XTS
- Complies with IEEE 1619-2007 and NIST SP800-38E standards
- Performance selectable to meet or exceed USB 3.0 and SATA 3.0 (6 Gbps), even on low cost FPGA families
- Low area, implementation of AES-XTS suitable for data storage applications.
- Based on the NIST validated (Cert #953) AES-G3 implementation of FIPS 197 (November 2001) Advanced Encryption Standard
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AES Encryption Core with XTS
- Full Verilog core
- 128 or 256 bit selectable AES encryption
- The AES-XTS algorithm is FIPS-197 certified, cert. no 2408.
- The encode and decode channels are made to look and act like independent FIFOs for ease of integration. The control block has a register interface to be easily managed by a hardware state machine or controlled by a processor for operations such as key initialization, and TWEAK configuration and management.
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Secure-IC's Securyzr™ Tunable AES (ECB, CBC, CTR, XTS, CCM, GCM) accelerator - optional SCA protection
- AMBA interface
- Supported key sizes: 128, 192 and 256 bits
- Multiple modes supported: ECB, CBC, CFB, OFB, CTR, CMAC, CCM, GMAC, GCM, XTS
- Compliant with NIST SP 800-38
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AES supporting ECB, CBC and XTS/XEX modes. Includes DMA and AXI interface.
- 100% AES compatible
- >2.4 GB/sec max throughput
- Up to 8 engines in parallel (configurable)
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Cryptographic co-processor for lightweight cryptography
- Support AES-XTS mode — IEEE Std 1619-2007 standard compliance
- Support 128 and 256-bit key size
- Random memory block access support
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DPA- and FIA-resistant Ultra High Bandwidth FortiCrypt AES IP core
- Ultra-high bandwidth due to multi-pipeline architecture, HUNDREDs Gbps (@500 MHz on a 45nm tech. process)
- Extensible pipeline architecture
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Advanced DPA- and FIA-resistant FortiCrypt AES SW library
- Ultra-strong side-channel and SIFA protection at high performance
- NIST FIPS-197 compliant
- AES-128/192/256 encryption and decryption
- Tunable protection level
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AES-XTS, Advanced Encryption Standard (256-bit key), XTS mode IP Core
- Moderate resource requirements: The entire XIP1183H requires 28456 Adaptive Lookup Modules (ALMs) (Intel Agilex F), and does not require any multipliers or DSPBlocks. Contact sales@xiphera.com for ASIC resource requirements.
- Performance: XIP1183H achieves an impressive throughput in the tens of Gbps range, for example 43.48+ Gbps in Xilinx Versal Prime.
- Standard Compliance: XIP1183H is compliant with both the Advanced Encryption Algorithm (AES) standard, and the XTS standard.
- Optional Ciphertext stealing support as defined in IEEE Std 1619-2018.
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AES-XTS, Advanced Encryption Standard (256-bit key), XTS mode IP Core
- Moderate resource requirements
- Performance
- Standard Compliance
