AES IP
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316
IP
from 69 vendors
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10)
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AHB AES with DMA
- The Advanced Encryption Standard (AES) IP Core is a complete hardware implementation encryption/decryption algorithm described in the U.S. Government Federal Information Processing Standards Publication 197 (FIPS 197).
- The AES IP Core implements the Rijndael algorithm which is a symmetric block cipher that can process 128-bit data blocks using 128, 192, or 256-bit cipher keys.
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AES - Encrypts sensitive data to ensure secure communication and transactions
- AES (Advanced Encryption Standard) is a widely-used encryption algorithm designed to secure sensitive data. It offers high levels of security with key sizes of 128, 192, or 256 bits and supports multiple encryption modes, ensuring robust protection for communications and transactions.
- AES is implemented in Verification IP (VIP) to verify cryptographic hardware modules in systems such as processors and communication devices. Its versatility makes it crucial for applications ranging from government communications to cloud storage and financial transactions
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AES GCM IP Core
- supports encryption and decryption
- supports offline and online key schedule
- supports 128, 192 and 256-bit key lengths
- has masked and non-masked modes
- supports encryption and decryption
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AES 256 encryption IP core
- Data Path runs at 256-bit width.
- Programming of Key and Initialization Vector Supported.
- Buffer-free implementation of RTL code is fast and easy to integrate into SoCs.
- Pipelined instances architecture with Vendor-independent code.
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Advanced Encryption Standard compliant with FIPS 197
- Support for 128 and 256 key bit length
- Support for ECB, CBC, CFB, OFB, CTR block cipher modes
- Internal key expansion module
- Flexible data read/write modes
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AES IP Core
- supports encryption and decryption for ECB, CBC, CTR mode of operations
- supports 128, 192, and 256-bit key lengths
- has masked and non-masked modes
- is compliant with FIPS 197
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AES Encrypt/Decrypt 128/192/256
- All Galois Field calculations are using 8 bit Primitive polynomial
- Key Calculation and data encryption done in parallel thus saving clock cycles
- Mode is run time programmable for each operation
- 128 bit data is encrypted with Key 128/192/256 bits.
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DPA- and FIA-resistant Ultra Low Power FortiCrypt AES IP core
- Ultra-low power in terms of performance per watt
- Ultra-strong side-channel attack protection (at least 1B traces)
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DPA- and FIA-resistant Ultra High Bandwidth FortiCrypt AES IP core
- Ultra-high bandwidth due to multi-pipeline architecture, HUNDREDs Gbps (@500 MHz on a 45nm tech. process)
- Extensible pipeline architecture
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DPA- and FIA-Resistant Balanced FortiCrypt AES IP Core
- A wide range of configurations to match the user’s cost/performance target
- Low latency
- Passes the rigorous Test Vector Leakage Assessment (TVLA) test at 1B traces
- Protected against fault injection attacks, including SIFA
