ADAS DSP IP
Filter
Compare
4
IP
from 1 vendors
(1
-
4)
-
Tensilica FloatingPoint KP1/KP6 DSPs
- VLIW parallelism issuing multiple concurrent operations per cycle
- Xtensa LX Secure Mode
- 128-bit and 512-bit SIMD
- IEEE 754 vector floating-point
-
Tensilica FloatingPoint KQ7/KQ8 DSPs
- VLIW parallelism issuing multiple concurrent operations per cycle
- 512-bit and 1024-bit SIMD
- IEEE 754 vector floating-point (HP, SP, DP)
- Performance-optimized fused multiply-add (FMA)
-
Tensilica ConnX 110/120
- Certified ISO 26262:2018 ASIL-compliant
- VLIW parallelism issuing multiple concurrent operations per cycle
- 128-bit or 256-bit SIMD
-
Tensilica ConnX B10/B20
- Single-instruction, multiple-data (SIMD) vector processing
- Up to 5-issue very long instruction word (VLIW) for parallel load/store, MAC, and ALU ops
